HT82D22R_10 Datasheet, PDF (24/41 Pages) Holtek Semiconductor Inc – 27MHz Two Channel RX 8-Bit MCU

HT82D22R/HT82D22A
There is a system clock control register implemented to select the clock used in the MCU. This register consists of the
USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK).
Bit No.
2~0, 7
3
4
5
6
Label R/W
Function
¾
¾ Undefined, should be cleared to ²0²
USBCKEN R/W
USB clock control bit. When this bit is set to ²1², it indicates that the USB clock is en-
abled. Otherwise, the USB clock is turned-off. (Default=²0²)
SUSP2
This bit is used to reduce power consumption in the suspend mode. In the normal
R/W
mode this bit must be cleared to zero (Default=0). In the HALT mode this bit should
be set high to reduce power consumption. If in USB mode set this bit LVR OPT must
disable
PS2_flag
R/W
This flag is used to show the MCU is under PS2 mode. (Bit=1)
This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²)
This bit is used to specify the system oscillator frequency used by the MCU. If a
SYSCLK R/W 6MHz crystal oscillator or resonator is used, this bit should be set to ²1². If a 12MHz
crystal oscillator or resonator is used, this bit should be cleared to ²0² (default).
SCC (1CH) Register
Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)
Register
Bits
Labels Read/Write Option
Functions
TBHP (0X1F)
3~0
PGC3~PGC0
R
¾
Store current table read bit11~bit8 data
27MHz FSK Receiver Function
There is two channel integrated RF transceiver designed for human interface devices (HID). Operating at 27MHz, it
provide frequency selection from 8 discrete channels via a parallel control PB1~PB3 or PC3, PD4, PD5, the frequency
range is 26.945~26.995MHz and channel spacing is 50kHz.
It provide power down to reduce power consumption by 27MHz FSK Receiver power down bit PD6/PB7 for
FSK-A/FSK-B. The optimized receiver design enables reception up to 3kHz per channel. It supply demodulation output
data with PC0/PB0 for FSK-A/ FSK-B.
Register Bits
PD6
0
PC3
3
PD4
4
PD5
5
Labels
PD6
PC3
PD4
PD5
Read/Write
R/W
R/W
Option
¾
¾
Functions
27MHz FSK-A Receiver power down bit
When ²1² indicate FSK-A Receiver for power down
mode, otherwise for normal mode
Default value ²0²
Parallel control bit 2~bit 0
Communication spacing control
000: 26.995 MHz
001: 27.045 MHz
010: 27.095 MHz
011: 27.145 MHz
100: 27.195 MHz
101: 27.245 MHz
110: 27.295 MHz
111: 26.945 MHz
Note: 27MHz FSK-A Receiver Control Register PCC.6, PCC.3, PDC.4, PDC.5 must for be ²0², the other bits are re-
served for PCC (except PCC.0 for FSK-A data output ) and PDC.
27MHz FSK-A Control Register
Rev. 1.10
24
January 27, 2010