BS83B08-3 Datasheet, PDF (24/141 Pages) Holtek Semiconductor Inc – 8-Bit Touch Key Flash MCU

BS83B08-3/B12-3/B16-3/B16G-3/C24-3
8-Bit Touch Key Flash MCU
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Many of
these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation.
Device
BS83B08-3
BS83B12-3
BS83B16-3
BS83B16G-3
BS83C24-3
Capacity
160´8
288´8
288´8
512´8
Bank 0
60H~FFH
60H~FFH
60H~FFH
80H~FFH
Bank 1
¾
80H~FFH
80H~FFH
80H~FFH
Bank 2
¾
¾
¾
80H~FFH
Bank 3
¾
¾
¾
80H~FFH
General Purpose Data Memory
The second area of Data Memory is known as the General Purpose Data Memory, which is reserved
for general purpose use. All locations within this area are read and write accessible under program
control.
The overall Data Memory is subdivided into several banks for the devices. The Special Purpose Data
Memory registers are accessible in all banks, with the exception of the EEC register at address 40H,
which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved
by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is
the address 00H.
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section,
however several registers require a separate description in this section.
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to
the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the
registers indirectly will result in no operation.
Rev. 1.30
24
September 22, 2011