HT67F2350 Datasheet, PDF (207/292 Pages) Holtek Semiconductor Inc – Advanced A/D Flash MCU with LCD & EEPROM

HT67F2350/HT67F2360
HT67F2370/HT67F2390
Advanced A/D Flash MCU with LCD & EEPROM
Bit 2
Bit 1
Bit 0
RXIFn: Receive TXR_RXRn data register status
0: TXR_RXRn data register is empty
1: TXR_RXRn data register has available data
The RXIFn flag is the receive data register status flag. When this read only flag is "0",
it indicates that the TXR_RXRn read data register is empty. When the flag is "1", it
indicates that the TXR_RXRn read data register contains new data. When the contents
of the shift register are transferred to the TXR_RXRn register, an interrupt is generated
if RIEn=1 in the UnCR2 register. If one or more errors are detected in the received
word, the appropriate receive-related flags NFn, FERRn, and/or PERRn are set within
the same clock cycle. The RXIFn flag will eventually be cleared when the UnSR
register is read with RXIFn set, followed by a read from the TXR_RXRn register, and
if the TXR_RXRn register has no more new data available.
TIDLEn: Transmission status
0: data transmission is in progress (data being transmitted)
1: no data transmission is in progress (transmitter is idle)
The TIDLEn flag is known as the transmission complete flag. When this read only
flag is "0", it indicates that a transmission is in progress. This flag will be set to "1"
when the TXIFn flag is "1" and when there is no transmit data or break character being
transmitted. When TIDLEn is equal to 1, the TXn pin becomes idle with the pin state
in logic high condition. The TIDLEn flag is cleared by reading the UnSR register with
TIDLEn set and then writing to the TXR_RXRn register. The flag is not generated
when a data character or a break is queued and ready to be sent.
TXIFn: Transmit TXR data register status
0: character is not transferred to the transmit shift register
1: character has transferred to the transmit shift register (TXR_RXRn data register is
empty)
The TXIFn flag is the transmit data register empty flag. When this read only flag is
"0", it indicates that the character is not transferred to the transmitter shift register.
When the flag is "1", it indicates that the transmitter shift register has received a
character from the TXR_RXRn data register. The TXIFn flag is cleared by reading the
UARTn status register (UnSR) with TXIFn set and then writing to the TXR_RXRn
data register. Note that when the TXENn bit is set, the TXIFn flag bit will also be set
since the transmit data register is not yet full.
UnCR1 Register
The UnCR1 register together with the UnCR2 register are the UARTn control registers that are used
to set the various options for the UARTn function such as overall on/off control, parity control, data
transfer bit length, etc. Further explanation on each of the bits is given below.
Bit
Name
R/W
POR
Bit 7
7
6
5
4
3
2
1
0
UARTENn BNOn PRENn PRTn STOPSn TXBRKn RX8n TX8n
R/W
R/W
R/W
R/W
R/W
R/W
R
W
0
0
0
0
0
0
x
0
"x": unknown
UARTENn: UARTn function enable control
0: Disable UARTn; TXn and RXn pins are in a high impedance state.
1: Enable UARTn; TXn and RXn pins function as UARTn pins
The UARTENn bit is the UARTn enable bit. When this bit is equal to "0", the
UARTn will be disabled and the RXn pin as well as the TXn pin will be set in a high
impedance state. When the bit is equal to "1", the UARTn will be enabled and the
TXn and RXn pins will function as defined by the TXENn and RXENn enable control
bits. When the UARTn is disabled, it will empty the buffer so any character remaining
in the buffer will be discarded. In addition, the value of the baud rate counter will
be reset. If the UARTn is disabled, all error and status flags will be reset. Also the
TXENn, RXENn, TXBRKn, RXIFn, OERRn, FERRn, PERRn and NFn bits will be
Rev. 1.00
207
December 06, 2016