HT9172_09 Datasheet, PDF (2/14 Pages) Holtek Semiconductor Inc – DTMF Receiver

Pin Assignment
VP
VN
GS
VREF
IN H
PW DN
X1
X2
VSS
1
18
2
17
3
16
4
15
5
14
6
13
7
12
8
11
9
10
H T9172
1 8 D IP -A /S O P -A
VDD
R T /G T
EST
DV
D3
D2
D1
D0
OE
HT9172
Pin Description
Pin Name I/O
Internal
Connection
Description
VP
I
Operational
Amplifier
Operational amplifier non-inverting input
VN
I
Operational amplifier inverting input
GS
O
Operational amplifier output terminal
VREEF
O
VREF
Reference voltage output, normally V_DD/2
X1
I
The system oscillator consists of an inverter, a bias resistor and the required
X2
O
oscillator
on-chip load capacitor.
A standard 3.579545MHz crystal connected to the X1 and X2 terminals imple-
ments the oscillator function.
PWDN
I
CMOS IN
Pull-low
Active high. This enables the device to go into its power down mode and inhibits
the oscillator. This pin input is pulled low internally.
INH
I
CMOS IN
Pull-low
Active high. This inhibits the detection of tones representing characters A, B, C
and D. This pin input is pulled low internally.
VSS
¾
¾
Negative power supply, ground
OE
I
CMOS IN
Pull-high
D0~D3 output enable, active high
D0~D3
O
CMOS OUT
Tristate
Received data output terminals
OE=²H²: Output enable
OE=²L²: High impedance
Data valid output.
DV
O CMOS OUT When the device has received a valid DTMF tone, this line will go high; other-
wise it remains low.
EST
O CMOS OUT Early steering output - see Functional Description
RT/GT
I/O
CMOS IN/OUT
Tone acquisition time and release time can be set through connection with ex-
ternal resistor and capacitor.
VDD
¾
¾
Positive power supply, 2.5V~5.5V for normal operation
Rev. 1.01
2
February 23, 2009