HT12D_09 Datasheet, PDF (2/12 Pages) Holtek Semiconductor Inc – Low power and high noise immunity CMOS

Block Diagram
O SC2 O SC1
O s c illa to r
D iv id e r
D IN
B u ffe r
D a ta D e te c to r
S y n c . D e te c to r
C o m p a ra to r
HT12D/HT12F
D a ta S h ift
R e g is te r
L a tc h C ir c u it
D a ta
C o m p a ra to r
C o n tr o l L o g ic
T r a n s m is s io n G a te C ir c u it
B u ffe r
VT
A d d re s s
VDD VSS
Note: The address/data pins are available in various combinations (see the address/data table).
Pin Assignment
8 -A d d re s s
4 -D a ta
A0 1
18
A1 2
17
A2 3
16
A3 4
15
A4 5
14
A5 6
13
A6 7
12
A7 8
11
VSS 9
10
H T12D
1 8 D IP -A
VDD
VT
O SC1
O SC2
D IN
D 11
D 10
D9
D8
8 -A d d re s s
4 -D a ta
NC 1
20
A0 2
19
A1 3
18
A2 4
17
A3 5
16
A4 6
15
A5 7
14
A6 8
13
A7 9
12
V S S 10
11
H T12D
2 0 S O P -A
NC
VDD
VT
O SC1
O SC2
D IN
D 11
D 10
D9
D8
1 2 -A d d re s s
0 -D a ta
A0 1
18
A1 2
17
A2 3
16
A3 4
15
A4 5
14
A5 6
13
A6 7
12
A7 8
11
VSS 9
10
H T12F
1 8 D IP -A
VDD
VT
O SC1
O SC2
D IN
A 11
A 10
A9
A8
1 2 -A d d re s s
0 -D a ta
NC 1
20
A0 2
19
A1 3
18
A2 4
17
A3 5
16
A4 6
15
A5 7
14
A6 8
13
A7 9
12
V S S 10
11
H T12F
2 0 S O P -A
NC
VDD
VT
O SC1
O SC2
D IN
A 11
A 10
A9
A8
Pin Description
Pin Name
I/O
A0~A11 (HT12F)
I
A0~A7 (HT12D)
D8~D11 (HT12D) O
DIN
I
VT
O
OSC1
I
OSC2
O
VSS
¾
VDD
¾
Internal
Connection
Description
NMOS
Transmission Gate
Input pins for address A0~A11 setting
These pins can be externally set to VSS or left open.
Input pins for address A0~A7 setting
These pins can be externally set to VSS or left open.
CMOS OUT
Output data pins, power-on state is low.
CMOS IN
Serial data input pin
CMOS OUT
Valid transmission, active high
Oscillator
Oscillator input pin
Oscillator
Oscillator output pin
¾
Negative power supply, ground
¾
Positive power supply
Rev. 1.20
2
February 20, 2009