HT66FB570 Datasheet, PDF (193/248 Pages) Holtek Semiconductor Inc – A/D Flash USB MCU

HT66FB570
A/D Flash USB MCU
USB Interface
The USB interface is a 4-wire serial bus that allows communication between a host device and up
to 127 max peripheral devices on the same bus. A token based protocol method is used by the host
device for communication control. Other advantages of the USB bus include live plugging and
unplugging and dynamic device configuration. As the complexity of USB data protocol does not
permit comprehensive USB operation information to be provided in this datasheet, the reader should
therefore consult other external information for a detailed USB understanding.
The device includes a USB interface function allowing for the convenient design of USB peripheral
products.
Power Plane
There are three power planes for the device and they are USB SIE VDD, VDDIO and the MCU VDD.
For the USB SIE VDD it will supply power for all circuits related to USB SIE and is sourced from
pin "UBUS". Once the USB is removed from the USB interface and there is no power in the USB
BUS, the USB SIE circuit is no longer operational.
For the PA port, the power can be supplied by the VDD, V33O or VDDIO pin selected using the
PMPS register.
The VDDIO is pin-shared with PE0 and VREF pins .The VDDIO function can be selected by the
corresponding pin-shared function selection bits.
For the MCU VDD, it supplies power for all the device circuits except the USB SIE which is
supplied by UBUS.
USB Interface Operation
To communicate with an external USB host, the internal USB module has the external pins known
as UDP and UDN along with the 3.3V regulator output V33O. A Serial Interface Engine (SIE) decodes
the incoming USB data stream and transfers it to the correct endpoint buffer memory known as the
FIFO. The USB module has 8 endpoints, EP0 ~ EP7, and the FIFO size for each endpoint except
endpoint 0 can respectively be configured using the UFC0~UFC2 registers by application programs.
All endpoints except endpoint 0 can be configured to have 8, 16, 32 or 64 bytes together with the
FIFOn registers as the FIFO size. The endpoint 0 has 8-byte FIFO size. The endpoint 0 supports the
Control transfer while the endpoint 1 ~ endpoint 7 support the Interrupt or Bulk transfer.
As the USB FIFO is assigned from the last sector of the General Purpose Data Memory and has
a start address to the upper address, dependent on the FIFO size, if the corresponding data RAM
sector is used for both general purpose RAM and the USB FIFO, special care should be taken that
the RAM EQU definition should not overlap with the USB FIFO RAM address. The USB FIFO size
and definition for IN/OUT control depends upon the UFC0~UFC2, UFIEN and UFOEN registers.
Rev. 1.10
193
December 15, 2016