HT46R46E Datasheet, PDF (19/45 Pages) Holtek Semiconductor Inc – Cost-Effective A/D Type 8-Bit MCU

HT46R46E/HT46C46E
Bit No.
0
1
2~6
7
Label
ADCS0
ADCS1
¾
TEST
Function
Select the A/D converter clock source.
0, 0: f_SYS/2
0, 1: f_SYS/8
1, 0: f_SYS/32
1, 1: Undefined
Unused bit, read as ²0².
For internal test only.
ACSR (23H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr EADI
; disable ADC interrupt
mov a,00000001B
mov ACSR,a
mov a,00100000B
; setup the ACSR register to select f_SYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a
; and select AN0 to be connected to the A/D converter
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START
; reset A/D
clr START
; start A/D
Polling_EOC:
sz EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp polling_EOC
; continue polling
mov a,ADR
; read conversion result value from the ADR register
mov adr_buffer,a
; save result to user defined memory
:
:
jmp start_conversion
; start next A/D conversion
Example: using interrupt method to detect end of conversion
clr EADI
; disable ADC interrupt
mov a,00000001B
mov ACSR,a
; setup the ACSR register to select f_SYS/8 as the A/D clock
mov a,00100000B
mov ADCR,a
:
:
Start_conversion:
clr START
set START
clr START
clr ADF
set EADI
set EMI
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
; reset A/D
; start A/D
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
Rev. 1.30
19
July 19, 2005