HT86XXX Datasheet, PDF (18/28 Pages) Holtek Semiconductor Inc – 8-Bit Voice Synthesizer MCU

HT86XXX
If WS2, WS1, WS0 all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.6 sec-
onds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re -
set² only the PC and SP are reset to zero. To clear the
contents of the WDT (including the WDT prescaler),
three methods are adopted; external reset (external re-
set (a low level to RES), software instructions, or a HALT
instruction. The software instruction is ²CLR WDT² and
execution of the ²CLR WDT² instruction will clear the
WDT.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
Power down - HALT
The HALT mode is initialized by a HALT instruction and
results in the following:
The system oscillator will be turned off but the WDT os-
cillator keeps running (if the WDT oscillator is selected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and recount
again.
· All I/O ports maintain their their original status.
· The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². By examining the TO and PD
flags, the reason for the chip reset can be determined.
The PD flag is cleared when the system powers-up or
executes the ²CLR WDT² instruction, and is set when
the HAL T instruction is executed. The TO flag is set if
a WDT time-out occurs, and causes a wake-up that only
resets the PC and SP. The other maintain their original
status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by a mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two se-
quences may happen. If the related interrupt is disabled
or the interrupt is enabled by the stack is full, the pro-
gram will resume execution at the next instruction. If the
interrupt is enabled and the stack is not full, the regular
interrupt response takes place.
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be dis-
abled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
Reset
There are 3 ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the PC and SP, leaving the other cir-
cuits in their original state. Some registers remain un-
changed during any other reset conditions. Most
registers are reset to their ²initial condition² when the re-
set conditions are met. By examining the PD flag and
TO flag, the program can distinguish between different
²chip resets².
TO PD
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
Rev. 1.00
18
November 1, 2002