HT49R70A-1_12 Datasheet, PDF (18/44 Pages) Holtek Semiconductor Inc – LCD Type 8-Bit MCU

HT49R70A-1/HT49C70-1/HT49C70L
Reset
There are three ways in which reset may occur.
· RES is reset during normal operation
· RES is reset during HALT
· WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the ²initial condition² once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES Wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT Wake-up HALT
Note: ²u² stands for unchanged
V DD
100kW
0 .1 m F
RES
B a s ic
R eset
C ir c u it
V DD
0 .0 1 m F
100kW
10kW
0 .1 m F
RES
H i-n o is e
R eset
C ir c u it
Reset Circuit
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from a HALT state. Awaking from a HALT
state, an SST delay is added.
An extra option load time delay is added during reset
and power on.
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tS S T
Reset Timing Chart
H A LT
W DT
RES
W DT
T im e - o u t
R eset
O SC1
SST
1 0 - b it R ip p le
C o u n te r
E x te rn a l
W a rm R e s e t
C o ld
R eset
P o w e r - o n D e te c tio n
Reset Configuration
The functional unit chip reset status is shown below.
Program Counter 000H
Interrupt
Disabled
Prescaler, Divider Cleared
WDT, RTC,
Time Base
Cleared. After master reset,
WDT starts counting
Timer/event Counter Off
Input/output Ports Input mode
Stack Pointer
Points to the top of the stack
Timer/Event Counter
Two timer/event counters are implemented in the de-
vice. One of them contains an 8-bit programmable
count-up counter, the other contains a 16-bit program-
mable count-up counter.
The Timer/Event Counter 0 clock source may come
from the system clock or system clock/4 or RTC time-out
signal or external source. System clock source or sys-
tem clock/4 is selected by options.
The Timer/Event Counter 1 clock source may come
from TMR0 overflow or system clock or time base
time-out signal or system clock/4 or external source,
and the three former clock source is selected by options.
Using external clock input allows the user to count exter-
Rev. 2.40
18
July 30, 2012