HT47R20A-1 Datasheet, PDF (18/43 Pages) Holtek Semiconductor Inc – R-F Type 8-Bit MCU

HT47R20A-1/HT47C20-1
A/D Converter
Two channels of RC type A/D converter are imple-
mented in the HT47R20A-1/HT47C20-1. The A/D con-
verter contains two 16-bit programmable count-up
counter and the Timer A clock source may come from
the system clock, instruction clock or RTC output. The
timer B clock source may come from the external RC os-
cillator. The TMRAL, TMRAH, TMRBL, TMRBH is com-
posed of the A/D converter when ADC/TM bit (bit 1 of
ADRC register) is ²1².
The A/D converter timer B clock source may come from
channel 0 (IN0 external clock input mode, RS0~CS0 os-
cillation, RT0~CS0 oscillation, CRT0~CS0 oscillation
(CRT0 is a resistor), or RS0~CRT0 oscillation (CRT0 is
a capacitor) or channel 1 (RS1~CS1 oscillation,
RT1~CS1 oscillation or IN1 external clock input). The
timer A clock source is from the system clock, instruction
clock or RTC prescaler clock output decided by TMRC
register.
There are six registers related to the A/D converter, i.e.,
TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR.
The internal timer clock is input to TMRAH and TMRAL,
the A/D clock is input to TMRBH and TMRBL. The
OVB/OVA bit (bit 0 of ADCR register) decides whether
timer A overflows or timer B overflows, then the TF bit is
set and timer interrupt occurs. When the A/D converter
mode timer A or timer B overflows, the TON bit is reset
and stop counting. Writing TMRAH/TMRBH makes the
starting value be placed in the timer A/timer B and read-
ing TMRAH/TMRBH gets the contents of the timer
A/timer B. Writing TMRAL/TMRBL only writes the data
into a low byte buffer, and writing TMRAH/TMRBH will
write the data and the contents of the low byte buffer into
the timer A/timer B (16-bit) simultaneously. The timer
A/timer B is changed by writing TMRAH/TMRBH opera-
tions and writing TMRAL/TMRBL will keep timer A/timer
B unchanged.
Reading /TMRBH will also latch the TMRAL/TMRBL into
the low byte buffer to avoid the false timing problem.
Reading TMRAL/TMRBL returns the contents of the low
byte buffer. In other word, the low byte of timer A/timer B
can not be read directly. It must read the
TMRAH/TMRBH first to make the low byte contents of
timer A/timer B be latched into the buffer.
If the A/D converter timer A and timer B are count-
ing, the TMRAH, TMRAL, TMRBH and TMRBL can-
not be read or written. To avoid conflicting between
timer A and timer B, the TMRAH, TMRAL, TMRBH
and TMRBL registers should be accessed with
²MOV² instruction under timer A and timer B off con-
dition.
The bit4~bit7 of ADCR decides which resistor and ca-
pacitor compose an oscillation circuit and input to
TMRBH and TMRBL.
The TM0, TM1 and TM2 bits of TMRC define the clock
source of timer A. It is recommended that the clock
source of timer A use the system clock, instruction clock
or RTC prescaler clock.
The TON bit (bit 4 of TMRC) is set ²1² the timer A and
timer B will start counting until timer A or timer B over-
flows, the timer/event counter generates the interrupt
request flag (TF; bit 4 of INTC1) and the timer A and
timer B stop counting and reset the TON bit to ²0² at the
same time.
If the TON bit is ²1², the TMRAH, TMRAL, TMRBH
and TMRBL cannot be read or written. Only when
the timer/event counter is off and when the instruc-
tion ²MOV² is used could those four registers be
read or written.
Bit No.
0
1
2~3
4
5
6
7
Label
Function
In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt
OVB/OVA
which comes from timer A overflow or timer B overflow.
(0= timer A overflow; 1= timer B overflow)
In the timer/event counter mode, this bit is void.
ADC/TM
Defines 16 timer/event counters or RC type A/D converter is enabled.
(0= timer/event counter enable; 1= A/D converter is enabled)
¾
Unused bit, read as ²0².
Defines the A/D converter operating mode (M3, M2, M1, M0)
0000= IN0 external clock input mode
0001= RS0~CS0 oscillation (reference resistor and reference capacitor)
M0 0010= RT0~CS0 oscillation (resistor sensor and reference capacitor)
M1 0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor)
M2 0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor)
M3 0101= RS1~CS1 oscillation (reference resistor and reference capacitor)
0110= RT1~CS1 oscillation (resistor sensor and reference capacitor)
0111= IN1 external clock input mode
1XXX= Unused mode
ADCR (25H) Register
Rev. 1.70
18
June 14, 2005