HT66F016 Datasheet, PDF (17/116 Pages) Holtek Semiconductor Inc – Enhanced Flash Type 8-Bit MCU with EEPROM

HT66F016/HT66F017/HT68F016/HT68F017
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to their in-
ternal system architecture. The range of devices take
advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all instruction set operations, which carries
out arithmetic operations, logic operations, rotation, in-
crement, decrement, branch decisions, etc. The internal
data path is simplified by moving data through the Accu-
mulator and the ALU. Certain internal registers are im-
plemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O and A/D control sys-
tem with maximum reliability and flexibility. This makes
the device suitable for low-cost, high-volume production
for controller applications.
Clocking and Pipelining
The main system clock, derived from either a HXT,
HIRC or LIRC oscillator is subdivided into four internally
generated non-overlapping clocks, T1~T4. The Pro-
gram Counter is incremented at the beginning of the T1
clock during which time a new instruction is fetched. The
remaining T2~T4 clocks carry out the decoding and ex-
ecution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions here the contents of the Program Coun-
ter are changed, such as subroutine calls or jumps, in
which case the instruction will take one more instruction
cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
fS Y S
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m C o u n te r
PC
PC +1
PC +2
P ip e lin in g
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1
M O V A ,[1 2 H ]
2
C A LL D E LA Y
3
C P L [1 2 H ]
4
:
5
:
6 D E LA Y : N O P
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
Rev. 1.00
17
May 14, 2012