BH66F2470 Datasheet, PDF (161/223 Pages) Holtek Semiconductor Inc – Glucose Meter Flash MCU

BH66F2470
Glucose Meter Flash MCU
SPIA Communication
After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when
data is written to the SPIAD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into
the SPIAD register. The master should output an SCSA signal to enable the slave device before a
clock signal is provided. The slave data to be transferred should be well prepared at the appropriate
moment relative to the SCSA signal depending upon the configurations of the SACKPOLB bit and
SACKEG bit. The accompanying timing diagram shows the relationship between the slave data and
SCSA signal for various configurations of the SACKPOLB and SACKEG bits.
The SPIA will continue to function in certain IDLE Modes if the clock source used by the SPIA
interface is still active.
SCSA
SPIAEN=1, SACSEN=0 (External Pull-high)
SPIAEN, SACSEN=1
SCKA (SACKPOLB=1, SACKEG=0)
SCKA (SACKPOLB=0, SACKEG=0)
SCKA (SACKPOLB=1, SACKEG=1)
SCKA (SACKPOLB=0, SACKEG=1)
SDOA (SACKEG=0)
SDOA (SACKEG=1)
D7/D0 D6/D1 D5/D2 D4/D3 D3/D4 D2/D5 D1/D6 D0/D7
D7/D0 D6/D1 D5/D2 D4/D3 D3/D4 D2/D5 D1/D6 D0/D7
SDIA Data Capture
SCSA
Write to SPIAD
SPIA Master Mode Timing
SCKA (SACKPOLB=1)
SCKA (SACKPOLB=0)
SDOA
SDIA Data Capture
D7/D0 D6/D1 D5/D2 D4/D3 D3/D4 D2/D5 D1/D6 D0/D7
Write to SPIAD
(SDOA does not change until first SCKA edge)
SPIA Slave Mode Timing – SACKEG=0
Rev. 1.00
161
March 15, 2017