HT82M9BEE Datasheet, PDF (16/47 Pages) Holtek Semiconductor Inc – USB Mouse Encoder 8-Bit MCU with EEPROM

HT82M9BEE/HT82M9BAE
fS Y S /4
TM R 0
TM 1
TM 0
TE
D a ta B u s
T im e r /E v e n t C o u n te r 0 ^{R e lo a d}
P r e lo a d R e g is te r
TM 1
TM 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
TO N
T im e r /E v e n t
C o u n te r 0
Timer/Event Counter 0
O v e r flo w
to In te rru p t
f S Y S /4
TM R 1
TM 1
TM 0
TO N
D a ta B u s
TM 1
TM 0
TE
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
1 6 B its
T im e r /E v e n t C o u n te r
(T M R 1 H /T M R 1 L )
Timer/Event Counter 1
L o w B y te
B u ffe r
R e lo a d
O v e r flo w
to In te rru p t
operate until overflow occurs (a Timer/Event Counter 0/1
reloading will occur at the same time). When the
Timer/Event Counter 0/1 (reading TMR0/TMR1) is read,
the clock will be blocked to avoid errors. As clock blocking
may results in a counting error, this must be taken into
consideration by the programmer.
Input/Output Ports
There are 20 bidirectional input/output lines in the
microcontroller, labeled from PA to PC, which are
mapped to the data memory of [12H], [14H] and [16H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC and
PCC) to control the input/output configuration. With this
control register, CMOS/NMOS/PMOS output or Schmitt
trigger input with or without pull-high/low resistor struc-
tures can be reconfigured dynamically under software
control. To function as an input, the corresponding latch
of the control register must write a ²1². The input source
V DD
D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P o rt O u tp u t
C o n fig u r a tio n
R e a d D a ta R e g is te r
P A , P B 4 , P B 7 W a k e -u p
P A 6 /T M R 0
P A 7 /T M R 1
C o n tr o l B it
DQ
CK Q
S
P u ll- h ig h
D a ta B it
DQ
CK Q
S
M
U
X
P u ll- lo w
P A 0 ~ P A 5 , P A 6 /T M R 0 , P A 7 /T M R 1
P B 0~P B 3
P B 4 /S D A
P B 5~P B 6
P B 7 /S C L
P C 0~P C 3
P A , P B 4 , P B 7 W a k e - u p O p tio n
Input/Output Ports
Rev. 1.20
16
August 13, 2007