HT48RA0-6 Datasheet, PDF (16/45 Pages) Holtek Semiconductor Inc – Remote Type 8-bit MCU

HT48RA0-6
Remote Type 8-bit MCU
The WDT timer is designed to prevent a software malfunction or sequence jumping to an unknown
location with unpredictable results. The Watchdog Timer can be disabled by configuration option. If
the Watchdog Timer is disabled, all the executions related to the WDT result in no operation and the
WDT will lose its protection purpose. In this situation the logic can only be restarted by external logic.
A WDT overflow under normal operation will initialise a “chip reset” and set the status bit “TO”.
To clear the contents of the WDT prescaler, two methods are adopted, software instructions or a
HALT instruction. There are two types of software instructions. One type is the single instruction
“CLR WDT”, the other type comprises two instructions, “CLR WDT1” and “CLR WDT2”. Of
these two types of instructions, only one can be active depending on the configuration option “CLR
WDT times selection option”. If the “CLR WDT” is selected (i.e.. CLR WDT times equal one),
any execution of the CLR WDT instruction will clear the WDT. In case “CLR WDT1” and “CLR
WDT2” are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to
clear the WDT; otherwise, the WDT may reset the chip due to a time-out.
C le a r W D T
fS Y S /4
W DT O SC
(1 2 K R C )
M UX
fS
3 - b it C o u n te r
F r e q u e n c y D iv id e r
P r e s c a lle r
( 8 - b it)
C o n fig u r a tio n
O p tio n
S e le c to r
C o n fig u r a tio n
O p tio n
W D T T im e - o u t,
fS
2ⁿ
(n = 8 ~ 1 1 )
Power Down Operation – HALT
The Power-down mode is initialised by the HALT instruction and results in the following:
• The system oscillator will be turned off but the WDT oscillator remains running (if the WDT
oscillator is selected).
• The contents of the on-chip Data Memory and registers remain unchanged.
• WDT prescaler is cleared.
• All I/O ports maintain their original status.
• The PDF flag is set and the TO flag is cleared.
The system can quit the HALT mode by means of an external falling edge signal on all I/O ports.
By examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is
cleared when the system powers up or when a CLR WDT instruction is executed and is set when
the HALT instruction is executed. The TO flag is set if the WDT time-out occurs during normal
operation.
The I/O ports wake-up can be considered as a continuation of normal execution. Each bit in I/O port
can be independently selected to wake up the device by the code option. Awakening from an I/O
port stimulus, the program will resume execution of the next instruction.
Once a wake-up event(s) occurs, it takes 1024 tSYS (system clock periods) to resume normal
operation. In other words, a dummy cycle period will be inserted after the wake-up.
To minimize power consumption, all I/O pins should be carefully managed before entering the
HALT status.
Rev. 1.20
16
March 24, 2016