HT16C24 Datasheet, PDF (16/34 Pages) Holtek Semiconductor Inc – RAM Mapping 72*4/68*8/60*16 LCD Driver Controller

HT16C24/HT16C24G
LCD Bias Generator
The full-scale LCD voltage (VOP) is obtained from
(VLCD – VSS). The LCD voltage may be temperature
compensated externally through the Voltage supply to
the VLCD pin.
Fractional LCD biasing voltages, known as 1/3, 1/4 or
1/5 bias voltage, are obtained from an internal voltage
divider of five serial resistors connected between VLCD
and VSS. The specific resistor can be switched out of
circuits to provide a 1/3, 1/4 or 1/5 bias voltage level
configuration.
LCD Drive Mode Waveforms
• When the LCD drive mode is selected as 1/4 duty
and 1/3 bias, the waveform and LCD display is
shown as follows:
VL_VCLDCD
CCOOMM0 ₀
VL_VCLDC-_DV- oVpo/p3/3
VL_VCLDC-_D2- V2oVpo/p3/3
VS_VSSS
VL_VCLDCD
CCOOMM1 ₁
VL_VCLDC-_DV- oVpo/p3/3
VL_VCLDC-_D2- V2oVpo/p3/3
VS_VSSS
VL_VCLDCD
CCOOMM2 ₂
VL_VCLDC-_DV- oVpo/p3/3
VL_VCLDC-_D2- V2oVpo/p3/3
VS_VSSS
VL_VCLDCD
CCOOMM3 ₃
VL_VCLDC-_DV- oVpo/p3/3
VL_VCLDC-_D2- V2oVpo/p3/3
VS_VSSS
VL_VCLDCD
SESGEGn _n
VL_VCLDC-_DV- oVpo/p3/3
VL_VCLDC-_D2- V2oVpo/p3/3
VS_VSSS
VL_VCLDCD
SESGEGn+n1+1
VL_VCLDC-_DV- oVpo/p3/3
VL_VCLDC-_D2- V2oVpo/p3/3
VS_VSSS
VL_VCLDCD
SESGEGn+n2+2
VL_VCLDC-_DV- oVpo/p3/3
VL_VCLDC-_D2- V2oVpo/p3/3
VS_VSSS
VL_VCLDCD
SESGEGn+n3+3VV_LVCL^V_LCDCLD-^CD-2D_{-V-V2oVoVppoo//pp33//33}
VS_VSSS
tLCD
LCLCDDsesgemgmenetnt
S(tSoa(tntoae)nt1e)1
S(tSoa(tftoafe)ft2fe)2
Note: tLCD=1/fLCD
Waveforms for 1/4 Duty Drive Mode with 1/3 Bias (VOP=VLCD-VSS)
Rev. 1.30
16
April 02, 2012