HT68F20 Datasheet, PDF (159/210 Pages) Holtek Semiconductor Inc – Enhanced I/O Flash Type MCU 8-Bit MCU with EEPROM

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
External Interrupt
The external interrupts are controlled by signal transi-
tions on the pins INT0~INT3. An external interrupt re-
quest will take place when the external interrupt request
flags, INT0F~INT3F, are set, which will occur when a
transition, whose type is chosen by the edge select bits,
appears on the external interrupt pins. To allow the pro-
gram to branch to its respective interrupt vector ad-
dress, the global interrupt enable bit, EMI, and
respective external interrupt enable bit, INT0E~INT3E,
must first be set. Additionally the correct interrupt edge
type must be selected using the INTEG register to en-
able the external interrupt function and to choose the
trigger edge type. As the external interrupt pins are
pin-shared with I/O pins, they can only be configured as
external interrupt pins if their external interrupt enable
bit in the corresponding interrupt register has been set.
The pin must also be setup as an input by setting the
corresponding bit in the port control register. When the
interrupt is enabled, the stack is not full and the correct
transition type appears on the external interrupt pin, a
subroutine call to the external interrupt vector, will take
place. When the interrupt is serviced, the external inter-
rupt request flags, INT0F~INT3F, will be automatically
reset and the EMI bit will be automatically cleared to dis-
able other interrupts. Note that any pull-high resistor se-
lections on the external interrupt pins will remain valid
even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active
edge that will trigger the external interrupt. A choice of
either rising or falling or both edge types can be chosen
to trigger an external interrupt. Note that the INTEG reg-
ister can also be used to disable the external interrupt
function.
Comparator Interrupt
The comparator interrupt is controlled by the two inter-
nal comparators. A comparator interrupt request will
take place when the comparator interrupt request flags,
CP0F or CP1F, are set, a situation that will occur when
the comparator output changes state. To allow the pro-
gram to branch to its respective interrupt vector ad-
dress, the global interrupt enable bit, EMI, and
comparator interrupt enable bits, CP0E and CP1E, must
first be set. When the interrupt is enabled, the stack is
not full and the comparator inputs generate a compara-
tor output transition, a subroutine call to the comparator
interrupt vector, will take place. When the interrupt is
serviced, the external interrupt request flags, will be au-
tomatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
Multi-function Interrupt
Within these devices there are up to six Multi-function
interrupts. Unlike the other independent interrupts,
these interrupts have no independent source, but rather
are formed from other existing interrupt sources, namely
the TM Interrupts, SIM Interrupt, External Peripheral In-
terrupt, LVD interrupt and EEPROM Interrupt.
A Multi-function interrupt request will take place when
any of the Multi-function interrupt request flags,
MF0F~MF5F are set. The Multi-function interrupt flags
will be set when any of their included functions generate
an interrupt request flag. To allow the program to branch
to its respective interrupt vector address, when the
Multi-function interrupt is enabled and the stack is not
full, and either one of the interrupts contained within
each of Multi-function interrupt occurs, a subroutine call
to one of the Multi-function interrupt vectors will take
place. When the interrupt is serviced, the related
Multi-Function request flag, will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
However, it must be noted that, although the
Multi-function Interrupt flags will be automatically reset
when the interrupt is serviced, the request flags from the
original source of the Multi-function interrupts, namely
the TM Interrupts, SIM Interrupt, External Peripheral In-
terrupt, LVD interrupt and EEPROM Interrupt will not be
automatically reset and must be manually reset by the
application program.
Time Base Interrupts
The function of the Time Base Interrupts is to provide reg-
ular time signal in the form of an internal interrupt. They
are controlled by the overflow signals from their respec-
tive timer functions. When these happens their respec-
tive interrupt request flags, TB0F or TB1F will be set. To
allow the program to branch to their respective interrupt
vector addresses, the global interrupt enable bit, EMI and
Time Base enable bits, TB0E or TB1E, must first be set.
When the interrupt is enabled, the stack is not full and the
Time Base overflows, a subroutine call to their respective
vector locations will take place. When the interrupt is ser-
viced, the respective interrupt request flag, TB0F or
TB1F, will be automatically reset and the EMI bit will be
cleared to disable other interrupts.
Rev. 1.00
159
November 3, 2009