HT82A850R Datasheet, PDF (15/41 Pages) Holtek Semiconductor Inc – Audio MCU

HT82A850R
Timer/Event Counter
Two timer/event counters are implemented in the
microcontroller. Each timer contains a 16-bit program-
mable count-up counter whose clock may be sourced
from an external or internal clock source. The internal
clock source comes from f_SYS/4. The external clock in-
put allows external events to be counted, time intervals
or pulse widths to be measured, or to generate an accu-
rate time base. There are three registers related to
Timer/Event Counter 0, TMR0H, TMR0L and TMR0C,
and another three related to Timer/Event Counter 1,
TMR1H, TMR1L and TMR1C. When writing data to the
TMR0L and TMR1L registers, note that the data will only
be written into a lower-order byte buffer. The data will
not be actually written into the TMR0L and TMR1L reg-
isters until a write operation to the TMR0H and TMR1H
registers is implemented. Reading the TMR0L and
TMR1L registers will read the contents of the lower-or-
der byte buffer. The TMR0C and TMR1C registers are
the Timer/Event Counter control registers, which define
the operating mode, the count enable or disable and the
active edge.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is sourced from the
external TMR0 or TMR1 pin. The timer mode functions
as a normal timer with the clock source coming from the
internal clock. Finally, the pulse width measurement
mode can be used to count the high level or low level du-
ration of an external signal on pins TMR0 or TMR1,
whose counting is based on the internal clock source.
In the event count or timer mode, the timer/event coun-
ter starts counting from the current contents in the
timer/event counter and ends at FFFFH. Once an over-
flow occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag (T0F; bit 5 of INTC0, or T1F; bit 6 of INTC0).
In the pulse width measurement mode with the values of
the TON and TE bits equal to 1, after the TMR0 or TMR1
pin has received a transient from low to high, or high to
low if the TE bit is ²0², it will start counting until the TMR0
or TMR1 pin returns to its original level and resets the
TON bit. The measured result remains in the timer/event
counter even if the activated transient occurs again.
Therefore, only 1-cycle measurement is made. Not until
the TON bit is again set can the cycle measurement
re-function. In this operational mode, the timer/event
counter begins counting not according to the logic level
but to the transient edges. In the case of counter over-
flows, the counter is reloaded from the timer/event coun-
ter register and issues an interrupt request, as in the
other two modes, i.e., event and timer modes.
To enable a count operation, the Timer ON bit (TON; bit
4 of TMR0C or TMR1C) should be set to 1. In the pulse
width measurement mode, TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON bit can only be reset by
instructions. A Timer/Event Counter overflow is one of
the wake-up sources. No matter what the operational
mode is, writing a 0 to ET0I or ET1I disables the related
interrupt service.
If the timer/event counter is turned OFF, writing data to
the timer/event counter preload register will also reload
the data into the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter keeps op-
erating until an overflow occurs.
When the timer/event counter is read, the clock is
blocked to avoid errors, which may result in a counting
error. Blocking of the clock should be taken into account
by the programmer.
Bit No.
0~2, 5
3
4
6
7
Label
¾
TE
TON
TM0
TM1
Function
Unused bit, read as ²0²
Defines the TMR active edge of the timer/event counter
In Event counter mode (TM1, TM0)=(0, 1):
1=count on falling edge;
0=count on rising edge
In Pulse width measurement mode (TM1, TM0)=(1, 1):
1=start counting on the rising edge, stop on the falling edge;
0=start counting on the falling edge, stop on the rising edge
Enable/disable the timer counting (0=disable; 1=enable)
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH), TMR1C (11H) Register
Rev. 1.10
15
July 25, 2007