HT47C20_02 Datasheet, PDF (15/46 Pages) Holtek Semiconductor Inc – 8-Bit R-F Type Mask MCU

HT47C20
fS
D iv id e r
fS /2 ⁸
P r e s c a le r
R T2
R T1
R T0
8 to 1
M ux.
Real time clock
fS /2 ⁸ ~ fS /2 ^{1 5}
R T C In te rru p t
Power down operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following.
· The system oscillator will turn off but the WDT oscilla-
tor or RTC oscillator keeps running (if the WDT oscil-
lator or the real time clock is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT will be cleared and recounted again (if the
WDT clock comes from the WDT oscillator or the real
time clock oscillator).
· All I/O ports maintain their original status.
· The PD flag is set and the TO flag is cleared.
· LCD driver is still running by mask option (if the WDT
OSC or RTC OSC is selected).
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal
on port A or a WDT overflow. An external reset causes a
device initialization and the WDT overflow performs a
²warm reset². Examining the TO and PD flags, the rea-
son for chip reset can be determined. The PD flag is
cleared when the system power-up or executing the CLR
WDT instruction and is set when the HALT instruction is
executed. The TO flag is set if a WDT time-out occurs, it
causes a wake-up that only resets the PC and SP, the
others maintain their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If awakening from an interrupt, two sequences
may happen. If the related interrupt is disabled or the in-
terrupt is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, the regular interrupt
response takes place.
If an interrupt request flag is set to ²1² before entering
the HALT mode the wake-up function of the related in-
terrupt will be disabled.
Once a wake-up event occurs, it takes 1024 t_SYS (sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after the
wake-up. If the wake-up results from an interrupt ac-
knowledgment, the actual interrupt subroutine execu-
tion is delayed by one more cycle. If the wake-up results
in the next instruction execution, this will execute imme-
diately after a dummy period has finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
· There are three ways in which a reset may occur.
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm reset
that just resets the PC and SP leaving the other circuits
in their original state. Some registers remain unchanged
during any other reset conditions. Most registers are re-
set to the ²initial condition² when the reset conditions
are met. By examining the PD and TO flags, the pro-
gram can distinguish between different ²chip resets².
TO PD
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² means ²unchanged².
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra delay. There is an extra delay of 1024 system
clock pulses when the system awakes from the HALT
state or when the system powers up.
The functional unit chip reset status are shown below.
PC
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC, Time Base
Clear. After master reset,
begin counting
Timer/event Counter Off
Input/output Ports
Input mode
SP
Points to the top of the stack
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tS S T
Reset timing chart
Rev. 1.60
15
July 26, 2002