HT48R50A Datasheet, PDF (14/46 Pages) Holtek Semiconductor Inc – 8-Bit Microcontroller

HT48R50A-1
abled, the stack is not full and the T1F is set, a
subroutine call to location 0CH will occur. The
related interrupt request flag (T1F) will be re-
set and the EMI bit cleared to disable further
interrupts.
During the execution of an interrupt subroutine,
other interrupt acknowledge signals are held
until the "RETI" instruction is executed or the
EMI bit and the related interrupt control bit are
set to 1 (if the stack is not full). To return from
the interrupt subroutine, "RET" or "RETI" may
be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests the
following table shows the priority that is ap-
plied. These can be masked by resetting the
EMI bit.
No. Interrupt Source Priority Vector
a External Interrupt
1
04H
b
Timer/event
counter 0 overflow
2
08H
c
Timer/event
counter 1 overflow
3
0CH
The Timer/Event Counter 0/1 interrupt request
flag (/T1F), external interrupt request flag
(EIF), enable Timer/Event Counter 0/1 inter-
rupt bit (ET0I/ET1I), enable external interrupt
bit (EEI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC)
which is located at 0BH in the data memory.
EMI, EEI, ET0I and ET1I are used to control
the enabling/disabling of interrupts. These bits
prevent the requested interrupt from being ser-
viced. Once the interrupt request flags (T0F,
T1F, EIF) are set, they will remain in the INTC
register until the interrupts are serviced or
cleared by a software instruction.
It is recommended that a program does not
use the "CALL subroutine" within the inter-
rupt subroutine. Interrupts often occur in an
unpredictable manner or need to be serviced
immediately in some applications. If only one
stack is left and enabling the interrupt is not
well controlled, the original control sequence will
be damaged once the "CALL" operates in the in-
terrupt subroutine.
Oscillator configuration
There are 3 oscillator circuits in the
microcontroller.
V DD
O SC1
470pF
O SC1
O SC2
fS Y S /4
O SC2
N M O S O p e n D r a in
C r y s ta l O s c illa to r
R C O s c illa to r
( In c lu d e 3 2 7 6 8 H z )
System oscillator
All of them are designed for system clocks,
namely the external RC oscillator, the external
Crystal oscillator and the internal RC
oscillator, which are determined by ROM code
option. No matter what oscillator type is se-
lected, the signal provides the system clock.
The HALT mode stops the system oscillator
and ignores an external signal to conserve
power.
S y s te m C lo c k /4
R TC O SC
W DT
O SC
ROM
C ode
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W S 0~W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.10
14
July 2, 2001