HT83XXX_07 Datasheet, PDF (13/39 Pages) Holtek Semiconductor Inc – Q-Voice

HT83XXX
Bit No.
0
1
2
3
4
5
6~7
Label
C
AC
Z
OV
PDF
TO
¾
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
Unused bit, read as ²0²
Status (0AH) Register
The Internal Timer Counter 0 Interrupt is initialized by
setting the Timer Counter 0 interrupt request flag (T0F:bit
5 of INTC), caused by a Timer Counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The Internal Timer Counter 1 Interrupt is initialized by
setting the Timer Counter 1 interrupt request flag (T1F:bit
6 of INTC), caused by a Timer Counter 1 overflow. When
the interrupt is enabled, and the stack is not full and the
T1F bit is set, a subroutine call to location 0CH will occur.
The related interrupt request flag (T1F) will be reset and
the EMI bit cleared to disable further interrupts.
Time Base Interrupt is triggered by set INTC.1 (ETBI)
which sets the related interrupt request flag (TBF:bit 4 of
INTC). When the interrupt is enabled, and the stack is not
full and the external interrupt is active, a subroutine call to
location 04H will occur. The interrupt request flag (TBF)
and EMI bits will be cleared to disable other interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgment are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to ²1² (of course, if the stack
is not full). To return from the interrupt subroutine, the
²RET² or ²RETI² instruction may be invoked. RETI will
set the EMI bit to enable an interrupt service, but RET
will not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The Timer Counter 0/1 interrupt request flag (T0F/T1F)
which enables Timer Counter 0/1 control bit (ET0I/ ET1I),
the time base interrupt request flag (TBF) which enables
time base control bit (ETBI) from the interrupt control reg-
ister (INTC:0BH) EMI, ETBI, ET0I, ET1I are used to con-
trol the enabling/disabling of interrupts. These bits
prevent the requested interrupt begin serviced. Once the
interrupt request flags (T0F, T1F, TBF) are set, they will
remain in the INTC register until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well con-
trolled, once a CALL subroutine if used in the interrupt
subroutine will corrupt the original control sequence.
Bit No. Label
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
ETBI
Controls the time base interrupt
(1= enabled; 0= disabled)
2
ET0I
Controls the timer 0 interrupt
(1= enabled; 0= disabled)
3
ET1I
Controls the timer 1 interrupt
(1= enabled; 0= disabled)
4
TBF
Time base interrupt request flag
(1= active; 0= inactive)
5
T0F
Timer 0 request flag
(1= active; 0= inactive)
6
T1F
Timer 1 request flag
(1= active; 0= inactive)
7
¾ Unused bit, read as ²0²
INTC (0BH) Register
Rev. 1.20
13
May 17, 2007