HT83R074 Datasheet, PDF (13/38 Pages) Holtek Semiconductor Inc – Q-Voice

HT83R074
Interrupt Source
Time Base Interrupt
Timer Counter 0 Overflow
Timer Counter 1 Overflow
Priority Vector
1
04H
2
08H
3
0CH
Oscillator Configuration
The HT83R074 provides two oscillator circuits for sys-
tem clock, i.e., RC oscillator and Crystal oscillator. No
matter what type of oscillator.. The signal is used for the
system clock. The HALT mode stops the system oscilla-
tor to conserve power. If the RC oscillator is used, an ex-
ternal resistor between OSC1 and VSS is required, and
the range of the resistance should be from 144kW to
275kW. The system clock, divided by 4. The RC oscilla-
tor provides the most cost effective solution. However,
the frequency of the oscillation may vary with VDD, tem-
perature, and the chip itself due to process variations. It
is therefore not suitable for timing sensitive operations
where accurate oscillator frequency is desired.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
O SC1
V DD ^{O S C 1}
O SC2
fS Y S /4
C r y s ta l O s c illa to r
O SC2
R C O s c illa to r
System Oscillator
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by options. This timer is
designed to prevent a software malfunction or sequence
jumping to an unknown location with unpredictable re-
sults. The Watchdog Timer can be disabled by option. If
the Watchdog Timer is disabled, all the executions re-
lated to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with pe-
riod 78ms normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approxi-
mately 20ms. This time-out period may vary with tem-
perature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
If WS2, WS1, WS0 all equal to 1, the division ratio is up to
1:128, and the maximum time-out period is 2.6 seconds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re -
set² only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset
(external reset (a low level to RES), software instruc-
tions, or a ²HALT² instruction. The software instruction
is ²CLR WDT² and execution of the ²CLR WDT² instruc-
tion will clear the WDT.
WS7
¾
¾
¾
¾
¾
¾
¾
¾
WS6
¾
¾
¾
¾
¾
¾
¾
¾
WS5
¾
¾
¾
¾
¾
¾
¾
¾
WS4
WS3
WS2
¾
¾
0
¾
¾
0
¾
¾
0
¾
¾
0
¾
¾
1
¾
¾
1
¾
¾
1
¾
¾
1
WDTS (09H) Register
WS1
0
0
1
1
0
0
1
1
WS0
0
1
0
1
0
1
0
1
Division Ratio
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Rev. 1.00
13
May 17, 2007