HT66F317 Datasheet, PDF (122/198 Pages) Holtek Semiconductor Inc – Enhanced A/D MCU with LCD Driver

HT66F317/HT66F318
Enhanced A/D MCU with LCD Driver
A/D Operation
The START bit is used to start and reset the A/D converter. When the microcontroller sets this bit
from low to high and then low again, an analog to digital conversion cycle will be initiated. When
the START bit is brought from low to high but not low again, the ADBZ bit in the SADC0 register
will be cleared to zero and the analog to digital converter will be reset. It is the START bit that is
used to control the overall start operation of the internal analog to digital converter.
The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion
process is in process or not. When the A/D converter is reset by setting the START bit from low
to high, the ADBZ flag will be cleared to “0”. This bit will be automatically set to “1” by the
microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is
complete, the ADBZ will be cleared to “0”. In addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal
interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to
the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the ADBZ bit in the SADC0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by
the system clock fSYS, and by bits SACKS2~SACKS0, there are some limitations on the maximum
A/D clock source speed that can be selected. As the recommended value of permissible A/D clock
period, tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example,
if the system clock operates at a frequency of 4MHz, the SACKS2~SACKS0 bits should not be set
to “000”, “110” or “111”. Doing so will give A/D clock periods that are less than the minimum A/D
clock period or greater than the maximum A/D clock period which may result in inaccurate A/D
conversion values. Refer to the following table for examples, where values marked with an asterisk
* show where, depending upon the device, special care must be taken, as the values may be less than
the specified minimum A/D Clock Period.
fSYS
1MHz
2MHz
4MHz
8MHz
12MHz
16MHz
20MHz
SACKS2,
SACKS1,
SACKS0
=000
(fSYS)
1μs
500ns
250ns*
125ns*
83ns*
62.5ns*
50ns*
SACKS2,
SACKS1,
SACKS0
=001
(fSYS/2)
2μs
1μs
500ns
250ns*
167ns*
125ns*
100ns*
SACKS2,
SACKS1,
SACKS0
=010
(fSYS/4)
4μs
2μs
1μs
500ns
333ns*
250ns*
200ns*
A/D Clock Period (tADCK)
SACKS2,
SACKS1,
SACKS0
=011
(fSYS/8)
8μs
4μs
SACKS2,
SACKS1,
SACKS0
=100
(fSYS/16)
16μs*
8μs
SACKS2,
SACKS1,
SACKS0
=101
(fSYS/32)
32μs*
16μs*
2μs
4μs
8μs
1μs
667ns
500ns
400ns*
2μs
1.33μs
1μs
800ns
4μs
2.67μs
2μs
1.6μs
SACKS2,
SACKS1,
SACKS0
=110
(fSYS/64)
64μs*
32μs*
16μs*
8μs
5.33μs
4μs
3.2μs
SACKS2,
SACKS1,
SACKS0
=111
(fSYS/128)
128μs*
64μs*
32μs*
16μs*
10.67μs*
8μs
6.4μs
A/D Clock Period Examples
Rev. 1.20
122
December 13, 2016