HT82K94E_07 Datasheet, PDF (12/43 Pages) Holtek Semiconductor Inc – USB Multimedia Keyboard Encoder 8-Bit MCU

HT82K94E/HT82K94A
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-
ommended, since the HALT will stop the system clock.
WS2 WS1 WS0
Division Ratio
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
WDTS (09H) Register
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialize a ²warm reset²
and only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are employed; external reset
(a low level to RES), software instruction and a ²HALT²
instruction. The software instruction include ²CLR
WDT² and the other set - ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one can
be active depending on the ROM code option - ²CLR
WDT times selection option². If the ²CLR WDT² is se-
lected (i.e. CLRWDT times equal one), any execution of
the ²CLR WDT² instruction will clear the WDT. In the
case wherein ²CLR WDT1² and ²CLR WDT2² are cho-
sen (i.e. CLRWDT times is equal to two), these two in-
structions must be executed to clear the WDT,
otherwise, the WDT may reset the chip as a result of
time-out.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
· The contents of the on-chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on I/O ports or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or exe-
cuting the ²CLR WDT² instruction and is set when exe-
cuting the ²HALT² instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the oth-
ers remain in their original status.
The I/O ports wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
bit in the Port A can be independently selected to
wake-up the device by option. PB, PC and PD can also
be selected to wake-up the device by option. Upon
awakening from an I/O port stimulus, the program will
resume execution of the next instruction. If it awakens
from an interrupt, two sequence may occur. If the related
interrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
HALT mode, the wake-up function of the related inter-
rupt will be disabled. Once a wake-up event occurs, it
takes 1024 t_SYS (system clock period) to resume normal
operation. In other words, a dummy period will be in-
serted after a wake-up. If the wake-up results from an in-
terrupt acknowledge signal, the actual interrupt
subroutine execution will be delayed by one or more cy-
cles. If the wake-up results in the next instruction execu-
tion, this will be executed immediately after the dummy
period is completed.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
TO PDF
RESET Conditions
0
0 RES reset during power-up
u
u RES reset during normal operation
0
0 RES wake-up HALT
1
u WDT time-out during normal operation
1
1 WDT wake-up HALT
Note: ²u² stands for ²unchanged²
Rev. 1.50
12
October 11, 2007