HT82D22R Datasheet, PDF (12/41 Pages) Holtek Semiconductor Inc – 27MHz Two Channel RX 8-Bit MCU

HT82D22R/HT82D22A
by setting the Timer/Event Counter 1 interrupt request
flag (T1F; bit 6 of INTC), caused by a timer 1 overflow.
When the interrupt is enabled, the stack is not full and
the T1F is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (T1F) will be reset
and the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
USB interrupt
1
Timer/Event Counter 0 overflow 2
Timer/Event Counter 1 overflow 3
Vector
04H
08H
0CH
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), USB interrupt request flag (USBF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), enable
USB interrupt bit (EUI) and enable master interrupt bit
(EMI) constitute an interrupt control register (INTC) which
is located at 0BH in the data memory. EMI, EUI, ETI are
used to control the enabling/disabling of interrupts. These
bits prevent the requested interrupt from being serviced.
Once the interrupt request flags (TF, USBF) are set, they
will remain in the INTC register until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across XTAL_INA or XTAL_INB and
XTAL_OUTA or XTAL_OUTB is needed to provide the
feedback and phase shift required for the oscillator. No
other external components are required. In stead of a
crystal, a resonator can also be connected between
X T A L _ IN A
4 7 p F X T A L _ IN B
X TA L_O U TA
X TA L_O U TB
47pF
C r y s ta l O s c illa to r
System Oscillator
XTAL_INA or XTAL_INB and XTAL_OUTA or
XTAL_OUTB to get a frequency reference, but two ex-
ternal capacitors in XTAL_INA or XTAL_INB and
XTAL_OUTA or XTAL_OUTB are required.
The external crystal must use 12MHz but it operate in
6MHz system clock. The USB SIE function also operate
in 6MHz.
Both of aXTAL_INA or XTAL_INBnd XTAL_OUTA or
XTAL_OUTB pin must be connect a 47pF capacitor to
ground.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (sys-
tem clock divided by 4), determine by ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 31ms/5V normally) is selected, it is first divided
by 256 (8-stage) to get the nominal time-out period of
8ms/5V. This time-out period may vary with tempera-
tures, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s/5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are re-
served for user defined flags, which can only be set to
²10000² (WDTS.7~WDTS.3).
Rev. 1.00
12
November 6, 2009