HT48R063_12 Datasheet, PDF (12/96 Pages) Holtek Semiconductor Inc – Enhanced I/O Type 8-Bit OTP MCU

HT48R063/064/065/066/0662/067
Ta=25°C
Symbol
Parameter
f_LXT
System Clock (LXT)
Test Conditions
V_DD
Conditions
¾
¾
Min. Typ. Max. Unit
¾ 32768 ¾
Hz
f_TIMER
Timer Input Frequency
(TCn)
2.2V~5.5V
¾ 3.0V~5.5V
4.5V~5.5V
0
¾ 4000 kHz
0
¾ 8000 kHz
0
¾ 12000 kHz
f_LIRC
LIRC Oscillator
3V
¾
5
10
15 kHz
5V
¾
6.5
13 19.5 kHz
t_RES
External Reset Low Pulse Width ¾
¾
1
¾
¾
ms
For HXT/LXT
¾ 1024 ¾
t_SYS
t_SST
System Start-up time Period
¾ _{For ERC/IRC}
¾
2
¾
t_SYS
(By configuration option) _{¾ 1024 ¾}
t_SYS
t_INT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
t_LVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
RESTD Reset Delay Time
¾
¾
¾
100
¾
ms
Note:
1. t_SYS=1/f_SYS
2. *For f_ERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. For the HT48R064 device, the f_ERC parameter is not applicable.
4. For the HT48R064 device, the HIRC support 4MHz only and f_HIRC parameter of (5V, 3.0V~5.5V) is
applicable.
5. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Power-on Reset Characteristics
Symbol
Parameter
Test Conditions
V_DD
Conditions
V_POR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
RR_VDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
t_POR
Minimum Time for VDD Stays at
V_POR to Ensure Power-on Reset
¾
¾
Min. Typ. Max. Unit
¾
¾ 100 mV
0.035 ¾
¾ V/ms
1
¾
¾
ms
V DD
tP O R
R R VDD
V POR
T im e
Rev. 1.40
12
October 23, 2012