HT48E30 Datasheet, PDF (12/43 Pages) Holtek Semiconductor Inc – I/O Type 8-Bit MTP MCU With EEPROM

HT48E30
The registers status is summarized in the following table.
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
MP0
-xxx xxxx
-uuu uuuu
-uuu uuuu
MP1
-xxx xxxx
-uuu uuuu
-uuu uuuu
BP
0000 0000
0000 0000
0000 0000
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
Program
Counter
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
WDTS
0000 0111
0000 0111
0000 0111
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
INTC
--00 0000
--00 0000
--00 0000
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMRC
00-0 1000
00-0 1000
00-0 1000
PA
1111 1111
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
PBC
1111 1111
1111 1111
1111 1111
PC
--11 1111
--11 1111
--11 1111
PCC
--11 1111
--11 1111
--11 1111
PG
---- ---1
---- ---1
---- ---1
PGC
---- ---1
---- ---1
---- ---1
EECR
1000 ----
1000 ----
1000 ----
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
RES Reset
(HALT)
-uuu uuuu
-uuu uuuu
0000 0000
uuuu uuuu
000H
uuuu uuuu
--uu uuuu
0000 0111
--01 uuuu
--00 0000
xxxx xxxx
00-0 1000
1111 1111
1111 1111
1111 1111
1111 1111
--11 1111
--11 1111
---- ---1
---- ---1
1000 ----
WDT Time-out
(HALT)*
-uuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
000H
uuuu uuuu
--uu uuuu
uuuu uuuu
--11 uuuu
--uu uuuu
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
---- ---u
---- ---u
uuuu ----
Timer/Event Counter
Timer/event counters (TMR) is implemented in the
microcontroller. The timer/event counter contains an 8-bit
programmable count-up counter and the clock may come
from an external source or from the system clock.
Using the internal clock sources, there are 2 reference
time-bases for the timer/event counter. The internal
clock source can be selected as coming from f_SYS or by
options. Using an external clock input allows the user to
count external events, measure time internals or pulse
widths, or generate an accurate time base. While using
the internal clock allows the user to generate an accu-
rate time base.
The timer/event counter can generate PFD signals by
using external or internal clock and the PFD frequency
is determine by the equation f_INT/[2´(256-N)].
There are 2 registers related to the timer/event counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the start-
ing value be placed in the timer/event counter preload
register and reading TMR retrieves the contents of the
timer/event counter. The TMRC is a timer/event counter
control register, which defines some options.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the f_INT clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR). The
counting is based on the f_INT clock.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once over-
flow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt re-
quest flag (TF; bit 5 of INTC) at the same time.
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a tran-
sient from low to high (or high to low if the TE bits is ²0²)
Rev. 1.20
12
March 3, 2006