HT46R32 Datasheet, PDF (12/43 Pages) Holtek Semiconductor Inc – A/D Type 8-Bit OTP MCU with OPA

HT46R32/HT46R34
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 t_SYS (sys-
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the status.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the program counter and stack
pointer, leaving the other circuits in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condi-
tion² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish be-
tween different ²chip resets².
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
Program Counter 000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter Off
Input/Output Ports Input mode
Stack Pointer
Points to the top of the stack
VDD
RES
S S T T im e - o u t
C h ip R e s e t
tS S T
Reset Timing Chart
V DD
0 .0 1 m F *
100kW
RES
10kW
0 .1 m F *
Reset Circuit
Note:
²*² Ensure that the length of the wiring, which is
connected to the RES pin is as short as possi-
ble, to avoid noise interference.
H A LT
W DT
W a rm R e s e t
RES
O SC1
SST
1 0 - b it R ip p le
C o u n te r
C o ld
R eset
S y s te m R e s e t
Reset Configuration
Rev. 1.10
12
March 16, 2007