HT16C23 Datasheet, PDF (12/35 Pages) Holtek Semiconductor Inc – RAM Mapping 56*4 / 52*8 LCD Driver Controller

HT16C23/HT16C23G
Functional Description
Power-On Reset
When the power is applied, the device is initialized by an internal power-on reset circuit. The status of the internal
circuits after initialization is as follows:
●● All common / segment outputs are set to VDD when VCCA2 pad is connected to VDD pad.
●● All common / segment outputs are set to VLCD when VCCA2 pad is connected to VLCD pad.
●● The drive mode 1/4 duty output and 1/3 bias is selected for 64 pin LQFP package.
●● The drive mode 1/8 duty output and 1/3 bias is selected for 48 pin LQFP package.
●● The System Oscillator and the LCD bias generator are off state.
●● LCD Display is off state.
●● Internal voltage adjustment function is enabled.
●● The Segment / VLCD shared pin is set as the Segment pin.
●● Detection switch for the VLCD pin is disabled.
●● Frame Frequency is set to 80Hz.
●● Blinking function is switched off
Data transfers on the I²C-bus should be avoided for 1 ms following power-on to allow completion of the reset
action.
Display Memory – RAM Structure
The display RAM is static 52 x 8-bits RAM which stores the LCD data. Logic “1” in the RAM bit-map indicates the
“on” state of the corresponding LCD segment; similarly, logic 0 indicates the ‘off’ state.
The contents of the RAM data are directly mapped to the LCD data. The first RAM column corresponds to the
segments operated with respect to COM0. In multiplexed LCD applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed with COM1, COM2 and COM3 respectively. The following
is a mapping from the RAM data to the LCD pattern:
Output
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
COM3
COM2
COM1
COM0
Output
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
COM3
COM2
COM1
COM0
address
00H
01H
02H
03H
04H
05H
SEG55
SEG54
1BH
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM mapping of 56x4 display mode
Rev. 1.10
12
June 21, 2011