HT45R34 Datasheet, PDF (11/41 Pages) Holtek Semiconductor Inc – C/R to F Type 8-Bit OTP MCU

S y s te m C lo c k /4
W DT
O SC
HT45R34
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
Watchdog Timer
W D T T im e - o u t
W S 0~W S 2
Power Down Operation
The Power Down mode is initialized by the ²HALT² in-
struction and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running, if the internal WDT oscillator
has been selected as the WDT source clock.
· The contents of the on chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has
been selected as the WDT source clock
· AlloftheI/Oportswillmaintaintheiroriginalstatus.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power Down mode by means
of an external reset, an interrupt, an external falling
edge signal on port Aor a WDT overflow. An external re-
set causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for the device reset can be de-
termined. The PDF flag is cleared by a system power-up
or executing the ²CLR WDT² instruction and is set when
a ²HALT² instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer; the other
registers maintain their their original status.
The port A and interrupt methods of wake-up can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected by configura-
tion options to wake-up the device. When awakened
from an I/O port stimulus, the program will resume exe-
cution at the next instruction. If it is awakened due to an
interrupt, two sequences may happen. If the related in-
terrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
Power Down Mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 t_SYS (system clock periods) to resume nor-
mal operation. A dummy period is therefore inserted af-
ter wake-up. If the wake-up results from an interrupt
acknowledgment, the actual interrupt subroutine execu-
tion will be delayed by one or more cycles. If the
wake-up results in the next instruction execution, this
will be executed immediately after the dummy period is
finished.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power Down
mode.
Reset
There are three ways in which a reset can occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
A WDT time-out, when the device is in the Power Down
mode, is different from other device reset conditions, in
that it can perform a ²warm reset² that resets only the
Program Counter and the Stack Poiner, leaving the
other circuits in their original state. Some registers re-
main unchanged during other reset conditions. Most
registers are reset to their ²initial condition² when the re-
set conditions are met. By examining the PDF and TO
flags, the program can distinguish between the different
device reset types.
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² means ²unchanged²
Rev. 1.20
11
October 15, 2007