HT32F52231 Datasheet, PDF (11/50 Pages) Holtek Semiconductor Inc – 32-Bit ARM Cortex-M0+ Microcontroller

32-Bit ARM^® Cortex™-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Single Channel Generation and Capture Timers – SCTM
■■ One 16-bit up and auto-reload counter
■■ One channel for each timer
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ Compare Match Output
■■ PWM waveform generation with Edge-aligned
■■ Single Pulse Mode Output
The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register
(CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be
used for a variety of purposes including general timer, input signal pulse width measurement or
output waveform generation such as single pulse generation or PWM output.
Basic Function Timer – BFTM
■■ One 32-bit compare/match count-up counter - no I/O control features
■■ One shot mode - counting stops after a match condition
■■ Repetitive mode - restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
Watchdog Timer – WDT
■■ 12-bit down counter with 3-bit prescaler
■■ Reset event for the system
■■ Programmable watchdog timer window function
■■ Register write protection function
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due
to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT delta value
register, WDT operation control circuitry and a WDT protection mechanism. If the software does
not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated
when the counter underflows. In addition, a reset is also generated if the software reloads the
counter when the counter value is greater than the WDT delta value. This means the counter must
be reloaded within a limited timing window using a specific method. The Watchdog Timer counter
can be stopped while the processor is in the debug mode. There is a register write protect function
which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
Rev. 1.51
11 of 50
April 11, 2017