HT46R068B_12 Datasheet, PDF (104/134 Pages) Holtek Semiconductor Inc – Enhanced A/D Type 8-bit OTP MCU

HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
SPIA registers
There are three registers which control the overall operation of the SPIA interface. These are the
SPIAD data registers and two control registers SPIAC0 and SPIAC1.
Register
Name
SPIAC0
SPIAC1
SPIAD
7
SASPI2
—
D7
6
SASPI1
—
D6
Bit
5
4
3
SASPI0
—
SACKPOL SACKEG
D5
D4
—
SAMLS
D3
SPIA Registers List
2
1
—
SPIAEN
SACSEN SAWCOL
D2
D1
0
—
SATRF
D0
The SPIAD register is used to store the data being transmitted and received. Before the device
writes data to the SPIA bus, the actual data to be transmitted must be placed in the SPIAD register.
After the data is received from the SPIA bus, the device can read it from the SPIAD register. Any
transmission or reception of data from the SPIA bus must be made via the SPIAD registers.
• SPIAD Register
Bit
7
6
5
4
3
2
1
0
Name
R/W
POR
SPD7
R/W
×
SPD6
R/W
×
SPD5
R/W
×
SPD4
R/W
×
SPD3
R/W
×
SPD2
R/W
×
SPD1
R/W
×
SPD0
R/W
×
“×” unknown
There are also two control registers for the SPIA interface, SPIAC0 and SPIAC1. Register SPIAC0
is used to control the enable/disable function and to set the data transmission clock frequency.
Register SPIAC1 is used for other control functions such as LSB/MSB selection, write collision
flag, etc.
• SPIAC0 Register
Bit
7
6
5
4
3
2
1
0
Name SASPI2 SASPI1 SASPI0
—
—
—
SPIAEN
—
R/W
R/W
R/W
R/W
—
—
—
R/W
—
POR
1
1
1
0
0
0
0
0
Bit 7~5
SASPI2~SASPI0: SPIA Master/Slave Clock Select
000: SPIA master, fSYS/4
001: SPIA master, fSYS/16
010: SPIA master, fSYS/64
011: SPIA master, fLXT
100: SPIA master, Timer 0 overflow/2 (PFD0)
101: SPIA slave
110: Reserved
111: Reserved
Bit 4~2
Bit 1
Bit 0
Unimplemented, read as “0”
SPIAEN: SPIA enable or disable
0: Disable
1: Enable
The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit
is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA
lines will lose their SPI function and the SPIA operating current will be reduced to a
minimum value. When the bit is high, the SPIA interface is enabled.
Unimplemented, read as “0”
Rev. 1.10
104
May 02, 2012