HT82V70 Datasheet, PDF (1/71 Pages) Holtek Semiconductor Inc – Two 6-Channel, up to 240MSPS CIS Timing Generator and Shading Correction

HT82V70
Two 6-Channel, up to 240MSPS
CIS Timing Generator and Shading Correction
Features
• 3.3V operating voltage
• Up to 240MSPS for two 6-channel inputs
• Programmable CIS module timing generator
• Image sensor shading correction
♦♦ _{0 ~ -255 8-bit dark shading (offset) correction}
♦♦ _{0.00x~8.00x 10-bit white shading (gain) correction}
♦♦ _{Embedded memory for up to 6 component coefficients}
of 1584 sensor elements
• Flexible frame start/stop control mechanism
• Provide Image line information
♦♦ _{line index}
♦♦ _{Left and right boundary of a line}
♦♦ _{max/min/summation/histogram information of a line}
• 8/16-bit image data output in VPFE or EMIF interface
• 3-wire/4-wire SPI interface
• 2-wire I²C interface
• Built in voltage comparator for roller input signal
• 100-pin LQFP package
Applications
• Double-sided scanner currency detectors
General Description
The HT82V70 is a fully integrated device for CIS
imaging application. It features programmable timing
generator and image sensor shading correction to
sample and condition the outputs of CIS (Contact
Image Sensor) arrays for high-speed double-sided
scanner applications.
With up to two AFE HT82V48 ICs, it can support
two 3~6-channel inputs up to 240MSPS. Intelligent
image sensor shading correction is then employed on
each sensor element. The sensor data can be not only
corrected but also averaged per line for black level
calculations. The Video Processing Front End (VPFE)
Interface multiplexed shaded ADC’s outputs two
high-bytes for each ADC’s output or one 16-bit wide
output for each ADC. A pixel clock PCLK transports
the 16-bit wide data to the output port.
The internal registers are programmed through a
2-wire I²C or 3-wire/4-wire SPI interface, for timing
control, gain, offset and operating mode adjustments.
Block Diagram
n = R/G/B/IR/UV/IR2
CIS1_SP
CIS1_MODE
CIS1_nLED
CIS_CLK
CIS2_SP
CIS2_MODE
CIS2_nLED
CIS1
DLL
I/F
CIS2
I/F
Shading
RAM
Timing
Generator
PLL
POR
LDO
SPI
AFE1_ADCK
AFE1_SHD
AFE1_CLP
AFE1_DIN[15:0]
AFE2_ADCK
AFE2_SHD
AFE2_CLP
AFE2_DIN[15:0]
AFE1
+
X
ISP1
V
I/F
P
LINE
BUF
M
U
X
I
F
/
E
AFE2
+
X
ISP2
M
I/F
I
F
MUX
A
ROLLER_IN
FRM_START
ROLLER_OUT
SCSN
SCK
SDI
SDO
PCLK_MWAIT
HD_MWEB
VD_MOEN
VP_D[15:0]
Rev. 1.00
1
January 12, 2017