HT48CA3 Datasheet, PDF (1/36 Pages) Holtek Semiconductor Inc – 8-Bit Remote Type MCU

HT48CA3
8-Bit Remote Type MCU
Features
· Operating voltage: 2.2V~3.6V
· 23 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler (TMR0)
· 16-bit programmable timer/event counter and
overflow interrupts (TMR1)
· On-chip crystal and RC oscillator
· Watchdog Timer
· 24K´16 program memory ROM
(8K´16 bits´3 banks)
· 224´8 data memory RAM
· PFD supported
· HALT function and wake-up feature reduce power
consumption
· 8-level subroutine nesting
· Up to 1ms instruction cycle with 4MHz system clock at
V_DD=3V
· Bit manipulation instruction
· 16-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· 28-pin SKDIP/SOP package
General Description
The HT48CA3 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications. The data ROM
can be used to store remote control codes. This device
is the mask version which is fully pin and functionally
compatible with the OTP version HT48RA3 device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
programmable frequency divider, HALT and wake-up
functions, as well as low cost, enhance the versatility of
this device to suit a wide range of application possibili-
ties such as industrial control, consumer products, sub-
system controllers, and particularly suitable for use in
products such as universal remote controller (URC).
Block Diagram
IN T /P F 0
P ro g ra m
ROM
P ro g ra m
C o u n te r
BP
STAC K
In te rru p t
C ir c u it
IN T C
In s tr u c tio n
R e g is te r
MP
M
U
X
D ATA
M e m o ry
In s tr u c tio n
D ecoder
T im in g
G e n e ra to r
O SC2
O SC1
RES
VDD
VSS
M UX
A LU
S h ifte r
STATU S
ACC
TM R 1C
M
U
TM R 1
X
fS Y S /4
TM R 1
TM R 0
TM R 0C
M
U
P r e s c a le r
fS Y S
X
TM R 0
E N /D IS
W D TS
W D T P r e s c a le r
W DT
M
U
fS Y S /4
X
PAC PO RT A
PA
W DT O SC
P A 0~P A 7
PFD
PBC _{PO RT B}
PB
P B 0~P B 7
PCC _{PO RT C}
PC
P C 0~P C 5
PFC
PO RT F
PF0
PF
Rev. 1.40
1
July 16, 2003