HT48C05 Datasheet, PDF (1/38 Pages) Holtek Semiconductor Inc – Cost-Effective I/O Type 8-Bit MCU

HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Cost-Effective I/O Type 8-Bit MCU
Features
· Operating voltage:
f_SYS=4MHz: 2.2V~5.5V
f_SYS=8MHz: 3.3V~5.5V
· 13 bidirectional I/O lines
· An interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with over-
flow interrupt and 8-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· Program memory ROM:
512´14 for HT48R05A-1/HT48C05
1024´14 for HT48R06A-1/HT48C06
· Data memory RAM
32´8 for HT48R05A-1/HT48C05
64´8 for HT48R06A-1/HT48C06
· Buzzer driving pair and PFD supported
· HALT function and wake-up feature reduce power
consumption
· Up to 0.5ms instruction cycle with 8MHz system clock
at V_DD=5V
· Allinstructionsinoneortwomachinecycles
· 14-bit table read instruction
· Two-level subroutine nesting
· Bit manipulation instruction
· Powerful instructions:
62 for HT48R05A-1/HT48C05
63 for HT48R06A-1/HT48C06
· Low voltage reset function
· 16-pin SSOP package
18-pin DIP/SOP package
General Description
The HT48R05A-1/HT48C05 and HT48R06A-1/
HT48C06 are 8-bit high performance, RISC architec-
ture microcontroller devices specifically designed for
cost-effective multiple I/O control product applications.
The mask version HT48C05 and HT48C06 are fully pin
and functionally compatible with the OTP version
HT48R05A-1 and HT48R06A-1 devices.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Block Diagram
IN T /P C 0
P ro g ra m
ROM
In s tr u c tio n
R e g is te r
P ro g ra m
C o u n te r
STAC K0
STAC K1
In te rru p t
C ir c u it
IN T C
PC0
MP
M
U
X
D ATA
M e m o ry
In s tr u c tio n
D ecoder
T im in g
G e n e ra to r
O SC2
O SC1
RES
VDD
VSS
M UX
A LU
S h ifte r
STATU S
ACC
TM R C
TM R
M
U
P r e s c a le r
fS Y S
X
T M R /P C 1
PC1
W D TS
M
W D T P r e s c a le r
W DT
U
X
fS Y S /4
PC C ^{PO RT C}
PC
B Z /B Z
PBC _{PO RT B}
PB
RC O SC
P C 0~P C 1
P B 0~P B 2
PAC _{PO RT A}
PA
P A 0~P A 7
Rev. 1.10
1
June 9, 2004