HT24LC64 Datasheet, PDF (1/10 Pages) Holtek Semiconductor Inc – CMOS 64K 2-WIRE SERIAL EEPROM

HT24LC64
Absolute Maximum Ratings
Operating Temperature (Commercial) ........................................................................................................ 0°C to 70°C
Storage Temperature ............................................................................................................................ -50°C to 125°C
Applied VCC Voltage with Respect to VSS .................................................................................V_SS -0.3V to V_SS+6.0V
Applied Voltage on any Pin with Respect to VSS _{................................................................................................}V_SS -0.3V to V_CC+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Symbol
Parameter
V_CC Operating Voltage
Test Conditions
V_CC
Conditions
¾
¾
Min.
2.4
I_CC1 Operating Current
5V Read at 100kHz
¾
I_CC2 Operating Current
5V Write at 100kHz
¾
V_IL Input Low Voltage
¾
¾
-1
V_IH
V_OL
I_LI
I_LO
I_STB1
I_STB2
C_IN
Input High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Standby Current
Standby Current
Input Capacitance (See Note)
¾
¾
2.4V I_OL=2.1mA
5V V_IN=0 or V_CC
5V V_OUT=0 or V_CC
5V V_IN=0 or V_CC
2.4V V_IN=0 or V_CC
¾ f=1MHz 25°C
0.7V_CC
¾
¾
¾
¾
¾
¾
C_OUT Output Capacitance (See Note) ¾ f=1MHz 25°C
¾
Note: These parameters are periodically sampled but not 100% tested.
Ta=0°C to 70°C
Typ.
Max.
Unit
¾
5.5
V
¾
2
mA
¾
5
mA
¾
0.3V_CC
V
¾
V_CC+0.5
V
¾
0.4
V
¾
1
mA
¾
1
mA
¾
5
mA
¾
4
mA
¾
6
pF
¾
8
pF
A.C. Characteristics
Ta=0°C to 70°C
Symbol
Parameter
Remark
Standard Mode* V_CC=5V±10%
Min. Max. Min. Max.
f_SK
Clock Frequency
¾
¾
100
¾
400
t_HIGH Clock High Time
¾
4000 ¾
600
¾
t_LOW Clock Low Time
¾
4700 ¾ 1200 ¾
t_R
SDA and SCL Rise Time
Note
¾ 1000 ¾
300
t_F
SDA and SCL Fall Time
Note
¾
300
¾
300
t_HD:STA START Condition Hold Time
After this period, the first
clock pulse is generated.
4000
¾
600
¾
t_SU:STA
START Condition Setup Time
Only relevant for repeated
START condition.
4000
¾
600
¾
t_HD:DAT Data Input Hold Time
¾
0
¾
0
¾
t_SU:DAT Data Input Setup Time
¾
200
¾
100
¾
t_SU:STO STOP Condition Setup Time
¾
4000 ¾
600
¾
t_AA
Output Valid from Clock
¾
¾ 3500 ¾
900
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.00
2
January 5, 2005