48E30 Datasheet, PDF (1/44 Pages) Holtek Semiconductor Inc – 8-Bit I/O Type MCU (With EEPROM)

Preliminary
HT48E30
8-Bit I/O Type MCU (With EEPROM)
Features
· Operating voltage:
f_SYS=4MHz: 2.2V~5.5V
f_SYS=8MHz: 3.3V~5.5V
· Low voltage reset function
· 23 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 2048´14 program memory ROM (MTP)
· 128´8 data memory EEPROM
· 96´8 data memory RAM
· Buzzer driving pair and PFD supported
General Description
The HT48E30 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
· HALT function and wake-up feature reduce power
consumption
· 4-level subroutine nesting
· Up to 0.5ms instruction cycle with 8MHz system clock
at V_DD=5V
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· 10⁶ erase/write cycles EEPROM data memory
· EEPROM data retention > 10 years
· All instructions in one or two machine cycles
· In system programming (ISP)
· 24/28-pin SKDIP/SOP package
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Block Diagram
IN T /P G 0
P ro g ra m
ROM
In s tr u c tio n
R e g is te r
P ro g ra m
C o u n te r
STAC K
4 L e v e ls
In te rru p t
C ir c u it
IN T C
PG 0
MP
M
U
X
D ATA
M e m o ry
In s tr u c tio n
D ecoder
T im in g
G e n e ra to r
O SC2
O SC1
RES
VDD
VSS
M UX
A LU
S h ifte r
STATU S
PG 1
PG 2
ACC
D a ta M e m o ry
EEPRO M
EECR
TM R 0
TM R 0C
M
fS Y S
M
P r e s c a le r
U
U
X
X
T M R /P C 0
W D TS
W D T P r e s c a le r
E N /D IS
W DT
fS Y S /4
M
U
X
W DT O SC
PAC PO RT A
PA
B Z /B Z
PBC _{PO RT B}
PB
P A 0~P A 7
P B 0~P B 7
PCC _{PO RT C}
PC
P C 0~P C 5
PG C _{PO RT G}
PG 0
PG
Rev. 0.00
1
January 12, 2004