HMC440QS16G_08 Datasheet, PDF (9/10 Pages) Hittite Microwave Corporation – 2.8 GHz INTEGER-N SYNTHESIZER

v03.0808
HMC440QS16G / 440QS16GE
2.8 GHz INTEGER-N SYNTHESIZER
(N = 2 - 32)
Synchronous Programming
For applications which can not tolerate a momentary undefined division ratio, which normally occurs while changing
the data bits (A0-A4) at random, synchronous programming can be used. Data is loaded into the counter on every
rising edge of the clock which occurs while the output (OUT) is “HIGH”. The typical minimum setup and hold times are
shown in the table below as a function of frequency. For precision applications, the rising edge of the complementary
output may be used to latch the new data bits (A0-A4), so that all bits are settled before the next load cycle.
T_{SETTLING MAX} = N/f_IN (For Synchronous Programming)
Where N is the desired division ratio, and f = Input Frequency (Hz)
IN
8
Parameter
t
SETUP
t
HOLD
0.5 GHz
200 ps
700 ps
1 GHz
200 ps
300 ps
2 GHz
200 ps
120 ps
Programmable Divider Timing Requirements
for Synchronous Programming
OUT
OUT
A0-A4
IN
C UR R E NT DATA
t
SU
t
HOLD
R ising E dge to
C lock New Data
NE W DATA
Data Load
R ising E dge
8 - 10
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