HMC624LP4_10 Datasheet, PDF (4/8 Pages) Hittite Microwave Corporation – 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL ATTENUATOR, DC - 6 GHz

v09.0210
HMC624LP4 / 624LP4E
0.5 dB LSB GaAs MMIC 6-BIT
DIGITAL ATTENUATOR, DC - 6 GHz
Timing Diagram (Latched Parallel Mode)
Parallel Mode
(Direct Parallel Mode & Latched Parallel Mode)
Note: The parallel mode is enabled when P/S is set to low.
Parameter
Typ.
Min. serial period, t_SCK
Control set-up time, t_CS
Control hold-time, t_CH
LE setup-time, t_LN
Min. LE pulse width, t_LEW
Min LE pulse spacing, t_LES
Serial clock hold-time from LE, t_CKN
Hold Time, t_PH.
Latch Enable Minimum Width, t_LEN
Setup Time, t_PS
100 ns
20 ns
20 ns
10 ns
10 ns
630 ns
10 ns
0 ns
10 ns
2 ns
Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch
Enable) must be at a logic high at all times to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the
LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the
desired states the LE is pulsed. See timing diagram above for reference.
Power-Up States
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D0-D5 determines
the power-up state of the part per truth table. The
attenuator latches in the desired power-up state
approximately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Bias Voltage
Vdd (V)
3
5
Control Voltage Table
Idd (Typ.) (mA)
1.8
2.0
State
Low
High
Vdd = +3V
0 to 0.5V @ <1 µA
2 to 3V @ <1 µA
Vdd = +5V
0 to 0.8V @ <1 µA
2 to 5V @ <1 µA
PUP Truth Table
LE
PUP1
PUP2
0
0
0
0
1
0
0
0
1
0
1
1
1
X
X
Relative Attenuation
-31.5
-24
-16
Insertion Loss
0 to -31.5 dB
Note: The logic state of D0 - D5 determines the
power-up state per truth table shown below when LE
is high at power-up.
Truth Table
Control Voltage Input
Reference
Insertion
D5
D4
D3
D2
D1
D0
Loss
High High High High High High
0 dB
High High High High High Low
-0.5 dB
High High High High Low High
-1 dB
High High High Low High High
-2 dB
High High Low High High High
-4 dB
High Low High High High High
-8 dB
Low High High High High High
-16 dB
Low Low Low Low Low Low -31.5 dB
Any combination of the above states will provide an attenuation
equal to the sum of the bits selected.
For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Phone: [phone] Fax: [phone] Order On-line at www.hittite.com
Application Support: Phone: [phone] or [e-mail]
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