HMC833LP6GE Datasheet, PDF (34/61 Pages) Hittite Microwave Corporation – Built in Digital Self Test

HMC833LP6GE
v01.1012
FRACTIONAL-N PLL WITH INTEGRATED VCO
25 - 6000 MHz
f_xtal
f_pd
As an example:
f_out
k
f_vco
f_xtal
R
f_pd
N_int
N_frac
Reg 04h
is the frequency of the reference oscillator input
is the PD operating frequency, f_xtal/R
1402.5 MHz
2
2,805 MHz
= 50 MHz
=1
= 50 MHz
= 56
= 0.1
= round(0.1 x 2²⁴) = round(1677721.6) = 1677722
50e6
1677722
f_VCO = ₁ (56 +
) = 2805 MHz + 1.92 Hz error
2²⁴
(EQ 15)
f_out = ^fVCO = 1402.5 MHz + 0.596 Hz error
2
(EQ 16)
In this example the output frequency of 1402.5 MHz is achieved by programming the 19-bit binary value
of 56d = 38h into intg_reg in Reg 03h, and the 24-bit binary value of 1677722d = 19999Ah into frac_reg in
Reg 04h. The 0.596 Hz quantization error can be eliminated using the exact frequency mode if required. In
this example the output fundamental is divided by 2. Specific control of the output divider is required. See
section 3.0 and description for more details.
1.12.2.2 Exact Frequency Tuning
Due to quantization effects, the absolute frequency precision of a fractional PLL is normally limited by
the number of bits in the fractional modulator. For example, a 24 bit fractional modulator has frequency
resolution set by the phase detector (PD ) comparison rate divided by 2²⁴. The value 2²⁴ in the denominator
is sometimes referred to as the modulus. Hittite PLLs use a fixed modulus which is a binary number. In
some types of fractional PLLs the modulus is variable, which allows exact frequency steps to be achieved
with decimal step sizes. Unfortunately small steps using small modulus values results in large spurious
outputs at multiples of the modulus period (channel step size). For this reason Hittite PLLs use a large
fixed modulus. Normally, the step size is set by the size of the fixed modulus. In the case of a 50 MHz PD
rate, a modulus of 2²⁴ would result in a 2.98 Hz step resolution, or 0.0596 ppm. In some applications it is
necessary to have exact frequency steps, and even an error of 3 Hz cannot be tol­erated.
Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can be
exactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some common
frequencies cannot be exactly represented. For example, N_frac = 0.1 = 1/10 must be approximated as
round((0.1 x 2²⁴)/ 2²⁴ ) ≈ 0.100000024. At f_PD = 50 MHz this translates to 1.2 Hz error. Hittite’s exact frequency
mode addresses this issue, and can eliminate quantization error by programming the channel step size to
F_PD/10 in Reg 0Ch to 10 (in this example). More generally, this feature can be used whenever the desired
frequency, f_VCO, can be exactly represented on a step plan where there are an integer number of steps
(<2¹⁴) across integer-N boundaries. Mathematically, this situation is satisfied if:
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