HMCAD1511 Datasheet, PDF (26/30 Pages) Hittite Microwave Corporation – High Speed Multi-Mode 8-Bit 30 MSPS to 1 GSPS A/D Converter

v03.0711
HMCAD1511
High Speed Multi-Mode 8-Bit
30 MSPS to 1 GSPS A/D Converter
Theory of Operation
HMCAD1511 is a multi Mode high-speed, CMOS ADC,
consisting of 8 ADC branches, configured in different
channel modes, using interleaving to achieve high
speed sampling. For all practical purposes, the device
can be considered to contain 4 ADCs. Fine gain is
adjusted for each of the eight branches separately.
HMCAD1511 utilizes a LVDS output, described in
‘Register Description, LVDS Output Configuration and
Control’. The clocks needed (FCLK, LCLK) for the
LVDS interface are generated by an internal PLL.
The HMCAD1511 operate from one clock input, which
can be differential or single ended. The sampling
clocks for each of the four channels are generated
from the clock input using a carefully matched clock
buffer tree. Internal clock dividers are utilized to con-
trol the clock for each ADC during interleaving. The
clock tree is controlled by the Mode of operations.
HMCAD1511 uses internally generated references.
The differential reference value is 1V. This results in
a differential input of −1V to correspond to the zero
code of the ADC, and a differential input of +1V to cor-
respond to the full-scale code (code 255).
The ADC employs a Pipeline converter architecture.
Each Pipeline Stage feeds its output data into the digi-
tal error correction logic, ensuring excellent differential
linearity and no missing codes.
HMCAD1511 operates from two sets of supplies and
grounds. The analog supply and ground set is identi-
fied as AVDD and AVSS, while the digital set is identi-
fied by DVDD and DVSS.
Interleaving Effects and Sampling Order
Interleaving ADCs will generate interleaving artifacts
caused by gain, offset and timing mismatch between
the ADC branches. The design of HMCAD1511 has
been optimized to minimize these effects. It is not
possible, though, to eliminate mismatch completely,
such that additional compensation may be needed,
especially when using high digital gain settings. The
internal digital fine gain control may be used to com-
pensate for gain errors between the ADC branches.
Due to the optimization of HMCAD1511 there is not
a one-to-one correspondence between the sampling
order, LVDS output order and the branch number.
Tables 23, 24 and 25 give an overview of the corre-
sponding branches, LVDS outputs and sampling order
for the different high speed modes.
Table 23: Quad Channel Mode
Channel #
Sampling
Order
LVDS Output
1
D1A
1
2
D1B
1
D2A
2
2
D2B
1
D3A
3
2
D3B
1
D4A
4
2
D4B
Fine Gain
Branch
1
2
3
4
5
6
7
8
Table 24: Dual Channel Mode
Channel #
Sampling
Order
LVDS Output
1
D1A
2
D1B
1
3
D2A
4
D2B
1
D3A
2
D3B
2
3
D4A
4
D4B
Fine Gain
Branch
1
3
2
4
5
7
6
8
Table 25: Single Channel Mode
Channel #
Sampling
Order
LVDS Output
1
D1A
2
D1B
3
D2A
4
D2B
1
5
D3A
6
D3B
7
D4A
8
D4B
Fine Gain
Branch
1
6
2
5
8
3
7
4
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [e-mail]
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