HMCAD1102 Datasheet, PDF (17/24 Pages) Hittite Microwave Corporation – Octal 12-Bit 80 MSPS A/D Co nverter

v03.0611
HMCAD1102
Octal 12-Bit 80 MSPS
A/D Converter
0
LVDS Clock Programmability and Data Output Modes
Name
Description
Default
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Address
In Hex
phase_ddr Controls the phase of LCLK
<1:0>
output relative to data.
90 degrees.
XX
42
btc_mode
Binary two’s complement format
for ADC output data.
Straight offset
binary.
X
msb_first
Serialized ADC output data
comes out with MSB first.
LSB-first
output.
X
en_sdr
Enable SDR output mode. LCLK
becomes a 12X input clock.
DDR output
mode.
X
46
fall_sdr
Controls whether the LCLK rising
or falling edge comes in the
middle of the data window when
operating in SDR mode.
Rising edge of
LCLK comes
in the middle
of the data
window.
X
1
The output interface of HMCAD1102 is normally a DDR interface, with the LCLK rising and falling edge transitions
in the middle of alternate data windows. The phase for LCLK can be programmed relative to the output frame clock
and data bits using phase_ddr<1:0>. The LCLK phase modes are shown in figure 9. The default timing is identical to
setting phase_ddr<1:0>=’10’.
PHASE_DDR<1:0>='00' (270 deg)
FCLK_N
FCLK_P
LCLK_P
LCLK_N
Dxx<1:0>
PHASE_DDR<1:0>='01' (180 deg)
FCLK_N
FCLK_P
LCLK_N
LCLK_P
Dxx<1:0>
PHASE_DDR<1:0>='10' (90 deg)
FCLK_N
FCLK_P
LCLK_N
LCLK_P
Dxx<1:0>
PHASE_DDR<1:0>='11' (0 deg)
FCLK_N
FCLK_P
LCLK_P
LCLK_N
Dxx<1:0>
Figure 8. Phase programmability modes for LCLK
The device can also be made to operate in SDR mode by setting the en_sdr bit to ‘1’. The bit clock (LCLK) is output
at 12x times the input clock in this mode, two times the rate in DDR mode. Depending on the state of fall_sdr, LCLK
may be output in either of the two manners shown in Figure 10. As can be seen in Figure 10, only the LCLK rising (or
falling) edge is used to capture the output data in SDR mode. The SDR mode is not recommended beyond 40 MSPS
because the LCLK frequency becomes very high.
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