HD74CDCV857 Datasheet, PDF (9/15 Pages) Hitachi Semiconductor – 2.5-V Phase-lock Loop Clock Driver

HD74CDCV857
Switching Characteristics
Item
Symbol Min
Typ
Max
Unit Test Conditions Notes
Period jitter
t _PER
–75
—
75
ps See figure 6, 9 7, 8
Half period jitter
t _HPER
–100 —
100
ps See figure 7, 9 8
Cycle to cycle jitter
t _CC
–75
—
75
ps See figure 5, 9
Static phase error
t _SPE
–50
—
50
ps See figure 3, 9 4, 5
Output clock skew
t _sk
—
—
100
ps See figure 4, 9
Operating clock frequency f_CLK(O)
60
—
200
MHz See figure 9
1, 2
Application clock
frequency
f _CLK(A)
95
133
170
MHz See figure 9
1, 3
Slew rate
t _SL
1.0
—
2.0
V/ns See figure 9
20% – 80%
PLL stabilization time
t _STAB
—
—
0.1
ms See figure 9
6
Notes: 1. The PLL must be able to handle spread spectrum induced skew (the specification for this
frequency modulation can be found in the latest Intel PC100 Registered DIMM specification)
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in
which it is not required to meet the other timing parameters.
3. Application clock frequency indicates a range over which the PLL must meet all timing
parameters.
4 Assumes equal wire length and loading on the clock output and feedback path.
5. Static phase error does not include jitter.
6. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its
feedback signal to its reference signal after power up.
7. Period jitter defines the largest variation in clock period, around anominal clock period.
8. Period jitter and half period jitter are independent from each other.
9