HM62W1400H Datasheet, PDF (7/14 Pages) Hitachi Semiconductor – 4M High Speed SRAM (4-Mword x1-bit)

HM62W1400H Series
Write Cycle
HM62W1400H
-12
-15
Parameter
Symbol Min Max Min Max Unit Notes
Write cycle time
t _WC
12
—
15
—
ns
Address valid to end of write
t _AW
8
—
10
—
ns
Chip select to end of write
t _CW
8
—
10
—
ns
9
Write pulse width
t _WP
8
—
10
—
ns
8
Address setup time
t _AS
0
—
0
—
ns
6
Write recovery time
t _WR
0
—
0
—
ns
7
Data to write time overlap
t _DW
6
—
7
—
ns
Data hold from write time
t _DH
0
—
0
—
ns
Write disable to output in low-Z
t _OW
3
—
3
—
ns
1
Output disable to output in high-Z
t _OHZ
—
6
—
7
ns
1
Write enable to output in high-Z
t _WHZ
—
6
—
7
ns
1
Note: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. Address should be valid prior to or coincident with CS transition low.
3. WE and/or CS must be high during address transition time.
4. if CS and OE are low during this period, Dout pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
output remains a high impedance state.
6. t_AS is measured from the latest address transition to the later of CS or WE going low.
7. t_WR is measured from the earlier of CS or WE going high to the first address transition.
8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low. A write ends at the earliest transition among CS going
high and WE going high. t_WP is measured from the beginnig of write to the end of write.
9. t_CW is measured from the later of CS going low to the the end of write.
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