HD74LV125A Datasheet, PDF (7/15 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates with 3-state Outputs

HD74LV125A
Switching Characteristics
• V_CC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Item
Propagation
delay time
Enable time
Disable
time
Symbol Min Typ
t_PLH
— 6.8
t_PHL
— 8.7
t_ZH
— 7.0
t_ZL
Max Min
13.0 1.0
16.5 1.0
13.0 1.0
— 8.8 16.5 1.0
t_HZ
— 5.1 14.7 1.0
t_LZ
— 7.3 18.2 1.0
Max
15.5
18.5
15.5
Unit Test Conditions
ns C_L = 15 pF
C_L = 50 pF
ns C_L = 15 pF
18.5
17.0
C_L = 50 pF
ns C_L = 15 pF
20.5
C_L = 50 pF
FROM
(Input)
A
OE
OE
TO
(Output)
Y
Y
Y
• V_CC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Item
Propagation
delay time
Enable time
Disable
time
Symbol Min Typ
t_PLH
— 4.8
t_PHL
— 6.1
t_ZH
— 4.8
t_ZL
Max Min
8.0 1.0
11.5 1.0
8.0 1.0
— 6.2 11.5 1.0
t_HZ
— 4.1 9.7 1.0
t_LZ
— 5.5 13.2 1.0
Max
9.5
13.0
9.5
Unit Test Conditions
ns C_L = 15 pF
C_L = 50 pF
ns C_L = 15 pF
13.0
11.5
C_L = 50 pF
ns C_L = 15 pF
15.0
C_L = 50 pF
FROM
(Input)
A
OE
OE
TO
(Output)
Y
Y
Y
7