HD404318 Datasheet, PDF (46/66 Pages) Hitachi Semiconductor – 4-bit HMCS400-series microcomputer

HD404318 Series
Transmit clock erors are detected as illustrated in figure 37.
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ← 0
SMR write
Yes
IFS = 1
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
State
Transmit clock
wait state
Transfer state
Transmit clock wait state
Transfer state
SCK pin (input)
SMR write
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit
clock error. When SMR
is written, IFS is set.
IFS
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
Transmit clock error detection procedure
Figure 37 Transmit Clock Error Detection
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