HD74AC4024 Datasheet, PDF (3/8 Pages) Hitachi Semiconductor – 7-State Binary Counter

Logic Diagram
Clock
Reset
HD74AC4024
CQ
CQ
CQ
CQ
RQ
RQ
RQ
RQ
Q1
Q2
Q3
Q4
DC Characteristics (unless otherwise specified)
Item
Symbol Max
Unit
Maximum quiescent supply current I_CC
80
µA
Maximum quiescent supply current I_CC
8.0
µA
Condition
V_IN = V_CC or ground, V_CC = 5.5 V,
Ta = Worst case
V_IN = V_CC or ground, V_CC = 5.5 V,
Ta = 25°C
AC Characteristics
Item
Maximum clock
frequency
Symbol
f _max
V_CC (V)*¹
3.3
5.0
Ta = +25°C
C_L = 50 pF
Min Typ
70
—
110 —
Propagation delay
t _PLH
3.3
Clock to Q₁
5.0
Propagation delay
t _PHL
3.3
Clock to Q₁
5.0
Propagation delay
t _PHL
3.3
Reset to outputs
5.0
1.0
9.5
1.0
7.0
1.0
9.5
1.0
6.5
1.0
10.5
1.0
7.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Max
—
—
12.5
9.0
12.0
9.0
12.5
10.0
Ta = –40°C to +85°C
C_L = 50 pF
Min
Max
60
—
95
—
1.0
13.5
1.0
9.5
1.0
13.0
1.0
10.0
1.0
13.5
1.0
11.0
Unit
MHz
ns
ns
ns
3