HD74AC373 Datasheet, PDF (3/11 Pages) Hitachi Semiconductor – Octal Transparent Latch with 3-State Output

Truth Table
Inputs
OE
LE
D_n
H
X
X
L
H
L
L
H
H
L
L
X
H : High Voltage Level
L : Low Voltage Level
Z : High Impedance
X : Immaterial
O₀ : Previous O₀ before Low-to-High Transition of Clock
HD74AC373/HD74ACT373
Outputs
O_n
Z
L
H
O₀
Functional Description
The HD74AC373/HD74ACT373 contains eight D-type latches with 3-state standard outputs. When the
Latch Enable (LE) input is High, data on the Dn inputs enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time its D input changes. When LE is Low, the
latches store the information that was present on the D inputs setup time proceding the High-to-Low
transition of LE. The 3-state standard outputs are controlled by the Output Enable (OE) input. When OE is
Low, the standard outputs are in the 2-state mode. When OE is High, the standard outputs are in the high
impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
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