HD74AC195 Datasheet, PDF (3/11 Pages) Hitachi Semiconductor – 4-bit Parallel-Access Shift Register

Timing Diagram
HD74AC195
CP
MR
J
K
PE
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Clear
H
L
H
L
Serial Shift
Load
Serial Shift
Mode Select-Function Table
Inputs
Outputs
Operating Modes
MR CP PE J
K
D_n
Q₀
Q₁
Q₂
Q₃
Q₃
Asynchronous Reset
L
X
XXXXL
L
L
L
H
Shift, Set First Stage
H
H
H
H
X
H
q₀
q₁
q₂
q₂
Shift, Reset First Stage H
H
L
L
X
L
q₀
q₁
q₂
q₂
Shift, Toggle First Stage H
H
H
L
X
q₀
q₀
q₁
q₂
q₂
Shift, Retain First Stage H
H
L
H
X
q₀
q₀
q₁
q₂
q₂
Parallel Load
H
L
X
X
d_n
d₀
d₁
d₂
d₃
d₃
H : HIGH Voltage Level
L : LOW Voltage Level
X : Immaterial
Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-
HIGH transition.
: LOW-to-HIGH clock transition.
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