HD74AC182 Datasheet, PDF (3/11 Pages) Hitachi Semiconductor – Carry Lookhead Generator

Logic Diagram
Cn G0 P0
G1 P1
G2 P2
HD74AC182/HD74ACT182
G3 P3
Cn+x
Cn+y
Cn+z
G
P
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Functional Description
The HD74AC182/HD74ACT182 carry lookahead generator accepts up to four pairs of Active Low Carry
Propagate (P₀ to P₃) and Carry Generate (G₀ to G₃) signals and an Active High Carry input (Cn) and
provides anticipated Active High carries (C_{n + x}, C_{n + y} , C_{n + z}) across four groups of binary adders. The
HD74AC182/HD74ACT182 also has Active Low Carry Propagate ( P) and Carry Generate (G) outputs
which may be used for further level of lookahead. The logic equations provided at the outputs are:
C_{n + x} = G₀ + P₀C_n
C_{n + y} = G₁ + P₁G₀ + P₁P₀C_n
C_{n + z} = G₂ + P₂G₁ + P₂P₁G₀ + P₂P₁P₀C_n
G = G₃ + P₃G₂ + P₃P₂G₁ + P₃P₂P₁G₀
P = P₃P₂P₁P₀
Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input
operand mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are
identical in both cases. Carries are rippled between lookahead blocks. The critical speed path follows the
circled numbers. There are several possible arrangements for the carry interconnects, but all achieve about
the same speed. A 28-bit ALU is formed by dropping the last HD74AC182/HD74ACT182.
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