HD74AC175 Datasheet, PDF (3/10 Pages) Hitachi Semiconductor – Quad D-Type Flip-Flop

HD74AC175
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q
outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their
individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and Q outputs to
follow. A Low input on the Master Reset (MR) will force all Q outputs Low and Q outputs High
independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
Inputs
Outputs
@ t_n, MR = H
@ t_n+1
Dn
Qn
Qn
L
L
H
H
H
L
H : High Voltage Level
L : Low Voltage Level
t_n : Bit Time before Clock Pulse
t_{n + 1}: Bit Time after Clock Pulse
Logic Diagram
MR CP D3
D2
D1
D0
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
Q3 Q3
Q2 Q2
Q1 Q1
Q0 Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
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